F to V converter problem

How about this one?

ftp://66.117.156.8/DoubleTach.jpg

John

I can't. Thanks to the NYAG and the danger of someone somewhere possibly seeing nakedness, my ISP no longer provides abse.

James Arthur

Decent.

I did a twin interleaved charge-dispenser thing, to cut drift. Not worth the bother in this case.

Cheers, James Arthur

It's a drift-over-temperature thing. Vf--the forward voltage of D1 and D2--changes with temperature.

That will change the voltage placed across C1, and how much of that voltage is input to the integrator U2.

Specifically, the effective voltage across C1 will increase about 5mV/ºC. For a 5v supply, that's a drift of +0.1%/ºC.

You might not care.

Cheers, James Arthur

No. Consider the circuit as dispensing small packages of charge from C1 at each input rising edge, and integrating those in C2. R2 bleeds off that charge at a controlled rate.

If you prefer, as input pulses come more quickly, the rectified pulses from C1 look more and more like a continuous current being fed into an inverting stage with a gain set by R2.

Cheers, James Arthur

Ahh very nice. I didn't quite 'get' how the ripple cancels when you described this before. But I see it now, (I think). You choose the one shot pulse time to be 1/2 the period of the "zero ripple frequency". This would imply that the maximum frequency is then twice the "zero ripple frequency". Is that correct?

George Herold

Yup.

Even at low frequencies, the ripple is less than a single-edge detector.

The HC123 is a retriggerable one-shot, so if the frequency goes past the design max limit, the output just hangs at +5, instead of getting erratic and goofy.

Of course you can add a fancier output filter if you please.

Or do it mostly digitally...

John

You have to wait (a day or 2 ?) then it can be seen. Jim's is there, now.

Ed

Thanks!

"The HC123 is a retriggerable one-shot, so if the frequency goes past the design max limit, the output just hangs at +5, instead of getting erratic and goofy."

Excellent! I was thinking about this on the ride home. If you gave up the ripple regection and let the two oneshots have different time constants you would have an F-V with a 'high' range at reduced sensitivity. I then thought about changing the sign of the shorter pulse. You've then got an F-V that has a maximum output voltage at some set frequency.

George Herold

Neat. A precise nonlinear breakpoint for very little effort.

John

Yeah I have no application for this, but you could imagine some motor control use. Does anyone make new designs with one-shots any more? I was talking with a FPGA designer a while back about a double pulser test circuit with a varible dealy time between the pulses. He got a far-away look in his eye and eventually said that yeah he could do it (Mind you I know nothing about FPGA's). When I mentioned using a couple of one- shots, he had heard of them, but hadn't thought of using them. (Ever problem looks like a nail when you're holding a hammer.)

George Herold

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=A0 =A0 =A0 =A0 =A0 || =A0 =A0 =A0C2

=A0 =A0 =A0.---||----. 390nF

=A0 =A0 =A0| =A0 || =A0 =A0|

=A0 =A0 =A0| =A0 ___ =A0 |

=A0 +--|___|--+

=A0 =A0 R2 =A0|

=A0|\\ 50k |

=A0 =A0 =A0| =A0>---+--> output

=A0 =A0 .----|+/

=A0 | =A0 =A0|/ =A0U2

=A0 | =A0 =A0 =A0 LM324

=A0 =A0 |

=3D =A0 =3D=3D=3D

GND

Thanks James,

It does effect my design. Will certainly take this into consideration.

George.

It's getting rare. We occasionally need an async delay within some fpga-based logic. For short, imprecise delays, a chain of gates will work, *if* you can persuade the compiler to leave them alone (not optimize them out) and not whine about them. For longer/more precise delays, we use an RC that's turned loose by a pin, charges up, and goes back into the fpga through various means.

One-shots are good for flashing led's. Classic async hairball logic is falling out of favor, as it should.

John