dumbest SPI chip

Microwire is, technically, a subset of SPI. We can certainly program the ARM's SPI port to talk to the AT93C86A.

Yeah, that would work. We know that the ARM will do simultaneous SPI output and input. We'd have to run a few cases to prove that everything works.

Or just bit-bang it.

This NXP chip has bizarre restrictions on pin use. Some are I/O; some are input only, some output only. The output-only pins power up in various high/low states. The SPI port I'm testing can't be repurposed to DIO. We've figured out most of the quirks, but we've been bit a few times. Some of the things we know about SPI had to be determined by experiment.

Hmmm, Still not enough information.

Is the code to test this port on the ARM chip or external to the ARM chip ??

I am sure you understand how an spi port works, so I use this page as a white board:

The second diagram shows Master and Slave devices. The master sends the slave a byte at the same time as the slave sends a byte to the master, exchanging data between master and slave.

The master always supplies the clock and chip select to the slave device.

Here is where my question comes from, which device is the master and which is the slave ?

Most times the sent data or received data is ignored for the sake of the transaction. I want to receive a byte so I'll send junk to the slave while the slave sends me real data. Or I want to send data to the slave, so it will send me data that II will ignore.

Looking at SPI code available on the net shows this type of simplex transactions.

So, there is no such thing as a dumb SPI chip.

thanks

don

Wire CS to the reset pin also. if you don't asert CS it you don't (eventually) get back what you sent, can test for that in software.

A small flash / eeprom memory? You could read the device ID. For testing you want to be able to do something usefull.

I second this but I would use something like a 25AA02E48 with the pre-programmed mac address. This gives you a known value on a read. You can check that a read of the OID matches the Microchip OID. You can also program the upper 1/4 with some values and then lock them down.

usermanual says they can, looking at the registers it does look like they can though with the limitation that some of the pins are output only

-Lasse

Since one end is an ARM processor with SPI interface, and the other end is the dumbest available SPI device, do you think that maybe I should make the ARM the master?

the usermanual say you have no choice, it is master only "dummest" possible spi device would be something like one or more '595 in string

spiclk,dout,din,ce to sclk,sin,sout,rclk

-Lasse

Yes,

As testing would require that ability to read/write multi-data, it would seem to be best that a spi memory device be used.

It would be self contained and you can write/read many times.

We have just upgraded our serial eeprom device (CAT25256) to a F-RAM device (FM25W256).

The cost for the F-RAM part is 5x the cost of the eeprom. But the life of the F-RAM part is almost forever (10^6 write cycles compared to 10^14 write cycles)

If you only need 2-3 for building your test fixture, I am sure you can get samples from Ramtron.com

hamilton

Let's see: at $3000 per DUT, one write cycle per test, 1e6 cycles, we wear out the test fixture after a mere $3 billion of revenue. Hmmm, we may have to consider a wear leveling algorithm.

LOL, I am sure your programmers would like to write more then one write cycle per test. Its just fun.

I am sure your investors would tolerate with only $1B in revenue !!

Remember, look after the pennies and the dollars will take care of themselves.

PICs and AVRs are slow. The LPC3250 is a 32-bit, 260 MHz ARM with vector floating point and all sorts of peripherial goodies. But I suspect they bought a bunch of outside IP (like DRAM controllers, ADC, ethernet, not to mention the ARM core itself) and sort of shoveled it all onto one chip.

It is already mentioned, but the 74HC595 IC and also the 74HC165 IC. I have used them quite a bit. NXP has the BQ package, which is the smallest I know of.

When chaining them, one has to be careful about the clock edge hold and setup times to the various units in the chain if it is to be guaranteed. At least, theoretically one has to be careful. If you only need 8 bits, you're in fat-city.

I have a 16-, 24-, and 40-bit loop-backed chains of 595/165 on the PCA I'll have released this summer. Never have any problems...

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test

So,

dual D-FF?

MISO; a 1-bit

to

Gee, you claim to be a business owner. How much does the LPC3250 cost relative to a PIC or ATtiny to be a minimal SPI device? Or did you lose context again, or is it a prejudice?

?-)