Domestic US source for small quantity of CA3127 transistor array?

Looks like there's stock out there in small quantities. I've had good success with Quest in the past, and Rochester Electronics is reputable.

I've got a tube of these (5 x NPN, RCA)--

Good enough?

Cheers, James Arthur

You could buy a couple of cheaper multipliers from AD.

George H.

I think you overestimate the thermal resistance of the oxide insulation. SOI is typically 200 nm of oxide (~1 W/m/K), so for a (say) 10-mil device, it adds only about 3 W/m/K between devices, which is about 1% of the thermal resistance of a SOT-packaged device.

Cheers

Phil Hobbs

A one-quadrant cuber only needs three transistors, so how about a MAT14?

See e.g.

Cheers

Phil Hobbs

Yabbut, ain't that Al2O3, single crystal because it conveniently aligns with silicon's lattice? Which is pretty conductive, not quite as good as Si, but suffice it to say -- good enough you can't even tell the difference (even less so than the above case!).

Or it's not SOI like I've heard it done, which, I haven't seen a drawing of the part in question, so I have no idea.

Tim

th

Si, but

Ah, Grasshopper, you conflate SOI with SOS. ;)

Silicon on Sapphire is an uber-expensive process once used by (iirc) HP and almost nobody else.

SOI is insulated with SiO2, either by wafer bonding followed by a lot of gr inding and polishing (old IBM), or by implanting some gross amount of oxyge n and then annealing to make the oxygen precipitates coalesce into an insul ating layer (SIMOX).

SOI parts are almost universally made on SIMOX-type wafers AFAIK.

Cheers

Phil Hobbs

Ah, yeah... that sounds much easier (and, better than "shit on [a] shingle"). :o)

Though now that you mention it...

Isn't single crystal Al2O3 pretty common? Like, sapphire plates are used for checkout scanners because it's scratch resistant (or at least, that was what I had heard, unless they use a very good scratch-resistant coating now)? Or is it that it has to be precisely axially aligned, low defect, and, ah, just as high purity as the Si that goes on top of it?

Two facts come to mind... Al2O3 has good ionic solubility and mobility (at only slightly elevated temperatures) for Na... which is also mobile in SiO2, leading to charge motion in gate oxides, and really shitty CMOS...

Tim

Nearly all my design activities for the past 10+ years have been with dielectrically isolated processes. The earlier processes had device thermal resistances of several thousand degrees per K, the newest one is even higher. I'd rather not have to even worry about it.

Thanks Steve

Hi James,

I'd completely forgotten about the CA3083 as I no longer have my antique NatSemi databooks (I gifted them to a friend). This would actually be preferable to the CA3127 as it's a lower-fT device and less prone to oscillation. The 5-transistor array gives me the option of a nifty translinear cuber or a "discrete" AD538.

I was playing with the numbers today and found that I^2.7 gives an even better fit than I^3 over my temperature range, so the AD538 approach may win after all. I don't really _need_ that level of accuracy but after decades of working with precision electronics...

Steve

Don't know what you mean by that--degrees per kelvin???

Cheers

Phil Hobbs

I'd be happy to send some your way ... my e-mail is valid.

Cheers, James Arthur

Oops, degrees K per watt. I was stupider than usual last night.

Advanced transistor models (Mextram is one) support individual transistor self-heating, which is extremely important in dielectrically isolated circuits. There's a global temperature variable to set the environment, but now each transistor's internal temperature can rise relative to the environment as a function of its instantaneous power dissipation, and this is taken account in setting all the temperature-dependent parameters for each device. This part of the model is fairly simple, a current source working into a parallel RC connected to thermal "ground", i.e. the environment, but the Mextram and other advanced models on the whole are way more complex than the basic Gummel-Poon model supported by most commonly-available simulators like PSPICE and LTSPICE, having about twice the number of parameters.

Taking this heating into account is important in precision circuits, even with junction-isolated processes, but you'll be doomed if you don't include it when working with DI where the self-heating can be more than an order of magnitude worse than in JI.

One challenge that's still out there is modeling the heat transfer between devices. This is actually a Very Hard Problem because it needs to be layout-aware. While there are a few researchers active in the area and occasionally publishing I'm not aware of any of this work making its way out of academia.

Steve

Several thousand K/W? For really small transistors, I'd believe that, but these array devices are pretty big.

Anyway, chuck in an op amp or two and use the three-transistor cuber I post ed upthread, with a MAT14. It has dramatically better matching and higher b eta than those old RCA things. Plus you can have your 2.7th power just by c hanging a resistor, and you'll have a spare transistor to use as a heater t o ovenize the die and get rid of drift.

Cheers

Phil Hobbs

Yes, dielectrically isolated transistors in a modern process can run several thousand K/W. It's at least an order of magnitude greater than for comparably-sized JI devices. The devices in the CA3083 are much larger and should run even cooler so I may not have to worry about it. I was thinking to use the spare transistor as a heater - that'll need additional control circuity, which can be added later, if I want to temperature-stabilize the thing.

I'd completely forgotten about the MAT-14. We might have some in the lab, it'll be interesting to compare them against the CA3083s that James is graciously sending me.

Steve

I'm still seriously skeptical that those sorts of numbers can apply to thes e large array transistors--their theta_JA is a good 50 times less than that . That 200 nm of oxide must be doing serious magic. I wish my house insulat ion were that good!

A reference would be a good place to start.

Cheers

Phil Hobbs

Sorry, Phil, I can't provide any references off the top of my head, though I know there've been papers in IEEE journals. There was one about modeling heat transfer between devices (the Very Hard Problem I mentioned) in the past few years, I'll see if I can dig it up.

Thousands of degrees per Watt is real, our model development guys routinely measure it as part of their work to develop models for new processes. You pretty much can't do any serious design in DI without taking temperature rise into account. Keep in mind these are small devices, say 0.35um x 5um emitters, 1-4 stripes and smaller. You're right that the relatively giant JI transistors in those old arrays probably have just a few percent of this thermal resistance.

Steve

Here's something I was able to find easily. I don't think it specifically mentions the high K/W for dielectrically isolated devices but it does address some of the subtleties in modeling multistripe and adjacent independent devices. I'll look around for more.

Walkey, Smy, Dickson, Zweidinger, and Fox: Equivalent Circuit Modeling of Static Subtrate Thermal Coupling Using VCVS Representation, JSSC Vol 37 No 9, pp. 1198-1206.

The sorts of K/W numbers I quoted are specific to the proprietary processes I work with but I imagine pretty much any modern dielectrically isolated complementary bipolar process will be in the same ballpark.

Steve