Distributed microcontroller computing

Oct 13, 2005 21 Replies

An 'appropriate' microcontroller that can handle that could cost as little as 50 cents (not counting its share of printed circuit board real estate, support components, power supply, etc). But consider a $200 desktop PC does 32 bit operations (four times as much data per operation) at about 2 gHz (100 times the speed of an 8-bit microcontroller), so offhand it looks like you're getting the same computational horsepower with one desktop PC as with 400 microcontrollers at the same cost.

You may be able to do better with 32-bit microcontrollers, or especially with FPGA's, but in any case you should always calculate the operations-per-dollar that each solution gives you.

Remember which, the Mandelbrot set or the AT?

There was a "Circuit Cellar" column in Byte many years (okay, a couple DECADES ago!) ago where Steve Ciarcia made a parallel-processor board using 8051's (or was it 8048's back then?), each running a floating-point math package, and each used to calculate points for the Mandelbrot set. ISTR there was one main processor to communicate with the PC and the other processors. Something like eight processors was as fast as a 286 (I forget if that's with or without a FP coprocessor), and you could put up to 64 processors on the board. This was neat toy, but still not very useful even back then.

They're "built in" to the main processor, starting with the 486. The cost per logic gate has continued to go down, so they've stuck more and more crap on/in the CPU.

Also, I'd be very suspicious, that if the code will split down like this, the SSE abilities in a modern PC could be used. It may be that the PC code, needs some more work using this sort of ability. I'd be suspicious that this sort of thought, coud bring perhaps three or more orders of magnitude improvement. As an example, I have a surface 'shaping' task, which written in C, and implemented using a normal PC, would require somthing over 1000hours to run. This was re-written to use SSE3, and implemented on an A64 X2, and solves in less than one second...

The other option, depending on what sort of 'code' structure is needed, is to implement the basic arithmetic in a FPGA, and have each one handle multiple cells. This would keep the gate count needed in the gate array down, below that neeed for a general purpose micro, and allow more cells per array. However even using the latter, a 8051 for example, is available as a general 'core' for use in such an array, with a less than 10K gate count, and cores are available now routinely, with 200K gates, operating at 500MHz, allowing a single chip to implement a 'macro cell' of perhaps

16 processors. Some of the basic PIC's are available in such a form, and it might well be possible to push 32 of the smaller designs into such a module.

Best Wishes

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