typically the PLL is a VCO which is divided and compared with a fixed clock, the microcontroller will program clock divider - it may even use an internal counter to do this. this divided clock is compared with a reference clock and the difference is fed back to control the VCO
probably some sort of quadrature encoder and a the micro just counts up or down as the knob is turned.
Many of the current designs are using Direct Digital Synthesis (DDS) instead of a PLL, though also PLL designs are used. The details of frequency set-up depend on the frequency generator chip (or chipset) chosen and the selected frequency generation scheme.
For a primer on DDS, see:
There are also links to chip datasheets and app notes for controlling them.
Most such radios have one or more PLL (phase lock loops) that add and multiply to produce the transmit and local oscillator frequency. For the TS-590S, you'll find a block diagram in the owners manual: The "in depth" manual includes a theory of operation section that explains how the PLL synthesizer works. In this radio, there are 3 mixers (triple conversion) that eventually produce the 24KHz IF used by the DSP. There is also a single conversion section for specific bands near the IF frequency. See Section 1.x for details.
For more detail and schematics, the full service manual is at:
The knob runs a shaft encoder that eventually sets multiple divider ratios (depending on frequency band) to produce the three local oscillator frequencies. The relationship is set by a formula that varies with the type of conversion, frequency range, and tx/rx. The divider ratios set the various PLL's to eventually generate the desired output frequency without also producing spurious and extraneous extra frequencies and noise.
There's more to HF radio design than just synthesizing the necessary frequencies. In my never humble opinion, the processor and synthesizer are the easiest parts of the puzzle. This might help:
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Jeff Liebermann jeffl@cruzio.com
150 Felker St #D http://www.LearnByDestroying.com
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