Digitally programmable 1MHz squarewave

He only needs the square wave. A DDS in an FPGA would be pretty easy, and he only needs 1 KHz steps. A DDS will have a period dither of just

+/- one clock cycle. With the available 80 MHz clock, that would be +/- 12.5 ns, or 1.25% of the nominal 1 MHz frequency. Many FPGAs have built-in clock multipliers, and could probably generate something like a 500 MHz clock internally from the 80 MHz clock. That will get a 2 Khz step. With a bit of fancy stuff, I think it would be possible to cut the resolution finer to get the required frequency steps. You could set up two clock multipliers at different frequencies, and select one or the other so that you get the desired output frequency.

Jon

Xilinx makes some VERY small FPGAs, and you only need a small number of I/O pins. DDS is VERY simple to code, you are talking literally about

20 lines of VHDL.

Jon

At it's simplest, it's just an adder and a latch. You could almost build that from ttl, though the delays around the adder would be a limiting factor...

Regards,

Chris

I was mentally ruling out FPGAs because of the 125C ambient, and thinking _scratch_ scratch -- i.e., 74HCxx logic. But Actel may have something, since they're kinda MIL-oriented. If they did, then a DDS based on that should work. A square wave out DDS would naturally dither the crossover point, which would keep the average frequency dead nuts on at the cost of considerable phase noise.

But never once have I heard the OP say "phase noise is an issue".

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

But do they work at 125C?

You could probably do this with a CPLD -- if you could find one that'd work at that temperature.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

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I thought he said "no dithering" isn't that phase noise?

George H.

d text -

The ON-Semiconductor MC100EP195 is a programmable delay generator

nominally offering 1023 possible delays ranging from 10psec to

10.23nsec.

Your 950kHz to 1.05MHz range of square wave outputs in 1kHz steps means intervals of from 476.2nsec to 526.3nsec between output transitions. One way of doing this would be with a 100MHz clock - to give you fixed periods from 470nsec to 520nsec in 10nsec steps - to which you would add appropriate delays in the range from 10psec to

10nsec in the MC100EP195.

I haven't thought this through properly, but I think you should be able to use a continuously accumulating accumulator to generate the 10- bit words that programmed each successive delay into the MC100EP195 to add the necessary low order delay onto to each clock edge coming out of the 6-bit counter dividing the 100MHz clock. The divisor being fed into the 6-bit counter would have to be incremented by one from time to time, whenever the total delay demanded from the MC100EP195 rolled over its 10nsec maximum delay.

Basically, this is a DDS algorithym. The 6-bit counter and the 10-bit delay generator need to be told the delay to the next clock edge at a maximum rate of 2.1MHz, which means that the accumulating accumulator can sit inside a cheap microcontroller.

The 16-bit number that it is spitting out has to be translated into ECL and latched to drive the inputs of the divider and the delay generator before they start setting up the next delayed clock edge. The MC100EP195 includes a latch to hold the programmed delay. It doesn't seem to be designed to generate different delay on successive clock edges, but you have at least 470nsec between edges, which is plenty of time to clean up after the last edge has been processed and set-up for the next edge.

The delays generated aren't all that precise, which will show up as an edge-jitter on the output - the (unrealistic) worst case is 1.16nsec (at maximum delay, with the delay generator moving from -40C to 85C). There's a subtlety in the way the nominal delays in the MC100195 have been chosen that might make 98.5MHz a better choice of clock frequency

You could cut down that edge-jitter quite a lot by going for a 500MHz clock - you could buy crystal controlled 500MHz clocks when I last looked, though they weren't cheap - and using nine bits of ECL synchonous counter to generate the rough delay in 2nsec steps, leaving the MC100EP195 to only generate from 0 to 2nsec of adjustable fine delay. Again, because the MC100EP195 is engineered to guarantee minimum delay step of more than 10psec and a programmable maximum delay of more than 10.23nsec, 492.5MHz might be a better choice of clock frequency for a typical MC100EP195.

The really hairy solution to the imperfections of the MC100EP195 is to use two of them, and continuously alternate one them into a delay measuring set-up where you use the device under test to generate a mark-to-space waveform and digitise the mean output voltages, which you can then translate into delays and program into a look-up table that translates the desired delay (in picoseconds) into the control code that will give the closest approximation to that delay. In principle you could alternate them a couple of times a second ...

The right DDS chip would do much the same job without demanding anything like the same amount of design time.

-- Bill Sloman, Nijmegen