Differential-pair amplifer

Win,

The article just showed up on PET.

It is in two parts. The first part is

SPICE Model Supports LDO Regulator Designs May 1, 2005

By Steven Sandler, Program Engineer, Acme Electric, Tempe, Ariz.

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The second part is

SPICE Model Supports LDO Regulator Design

Continuation of Article in Power Electronics Technology May 2005 By Steven M. Sandler and Charles E. Hymowitz

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(Caution - huge images)

Mike Monett

P.S. Replying to a post in google groups beta is an experience you do not want to experience more than once in your lifetime.

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mike
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Thanks, that's it. I found Sandler's technique easy to use, and it worked better than a similar method I had developed (out of desperation) using three to five series transistors.

--
 Thanks,
    - Win
Reply to
Winfield Hill

Thanks, Win. Do you have any guidance on correcting Sandler's parameters as mentioned above, or have you already discussed this in a different thread?

Mike Monett

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Mike Monett

I have just had a look at this, and I am a little confused. Sandler states "The results of the measurements were surprising, in that the Mosfet does not fit the primitive element for the SPICE Mosfet model."

Its very, very well known that ro (1/gds) of the mosfet acts the same as it does in bipolar, i.e. ro=Va/I, and spice models account for this. Certainly Bsim3 does.

I was so taken a back by this statement and thread, having designed LDOs at TI, that I just ran a few sims for sanity checks. Its like I am in a different world here.

In SS, of course, one simply does a dc run with op enabled, and plots of gds are available immediately.

So, spice models level 1, 2, 3 and BSim3.3 indeed all show the linear increase in gds as current is increased, although BSim3.3 starts off a little curved.

Whats going on here?

I looked at the AEI57230 mos .subckt. It has no value for lambda, so obviously it will not produce a gds as function of current. If lambda is zero, of course gds is always zero.

So, rather then building in extraneous circuits, simply set lambda.

What am I missing here? It seems to be the twilight zone.

Kevin Aylward snipped-for-privacy@anasoft.co.uk

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SuperSpice, a very affordable Mixed-Mode Windows Simulator with Schematic Capture, Waveform Display, FFT's and Filter Design.

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Kevin Aylward

Two comments. Typical power mosfets follow an Id ~ e^((Vgs-Vth)/nVT) relationship, rather than e^Vbe/VT that BJT transistors follow. The factor "n" is typically 3 to 5. Can this factor "n" be accounted for in the models? Second: Users are presented with a well-developed manufacturer's model, too often a level 1 model, and just need to fix the subthreshold region without unduly-disturbing the rest of the model. Adding Sandler's source-current-programmed diode is a quick solution.

They have the wrong slope. Dramatically so for level 1.

LAMBDA? Isn't that the drain-voltage adjustment parameter for current in the saturation region, Id = Isat / (1 - LAMBDA * Vds)? What's that have to do with the subthreshold current?

--
 Thanks,
    - Win
Reply to
Winfield Hill

Wrong language, poorly-written with respect to the subject perhaps, but the right region (note the current range in figure 3), and the right solution too, perhaps.

OK. That's wrong for our needs here, see below.

We (Sandler and myself) were both talking the subthreshold region, and for a moment it seemed you were as well when you said, "the mosfet acts the same as it does in bipolar..." Anyways, when using p-channel power mosfets in linear low-drop-out-voltage regulators, and when selecting a large FET to have good thermal conductance, one ends up working almost entirely in the subthreshold region. Ditto other linear applications. Most models completely miss the boat in this region, reporting out the wrong slope (too much transconductance) and the wrong operating voltage.

--
 Thanks,
    - Win
Reply to
Winfield Hill

Measure the MOSFET over many decades of current and determine the parameter "N" in the exponential equation (I use spreadsheet plots), plug it into the diode model, then trial-and-error reduce the FET's VTO term to match the current measured at a low value, like 100uA. I also edit the model, removing Ciss to outside the new gate diode.

--
 Thanks,
    - Win
Reply to
Winfield Hill

The BSim3 model has it all in the wash, so yes for that one. I'll have to check for the other ones. Probably does for level 3.

Ahh... the word "subthreshold" is not actually mentioned in the paper.

Ah... well, in subthreshold, yes. It would have helped if the paper actually explained what it was trying to do.

Yes. It sets the output impedance.

Oh? I am not talking about subthreshold current. Apparantly, you are.

I'll have a look at the models. I'll let you know what I rediscover:-)

Kevin Aylward snipped-for-privacy@anasoft.co.uk

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SuperSpice, a very affordable Mixed-Mode Windows Simulator with Schematic Capture, Waveform Display, FFT's and Filter Design.

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Kevin Aylward

Whoa! Actually, I'll refine my remark, it isn't so much just the subthreshold region one finds himself working in when using power MOSFETs for linear applications, as it is the transition region in which you found the discontinuity. Your painful plot is an example of what one frequently encounters with manufacturer's models.

--
 Thanks,
    - Win
Reply to
Winfield Hill

I did gloss over the fact that the current data was for a small range in Vgs, and what that implied. The bit that threw me though was the words of the "surprising" that data didn't fit the mosfet model, when the model was a level one. Level 1 is the basic model that from the outset ignores subthreshold, so it shouldn't be surprising that it fails to model gds in that region. Level 1 has Id = 0 for Vgs < Vt, so I just assumed one was discussing normal operation. Subthreshold is meaningless for level 1.

For Level 2 and Level 3, one might be forgiven as to what the details of the model are:-)

I did a little Gds plot of level=2

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Where it can be seen that the are two basic slopes, with a rather disconcerting discontinuity. around Vt. I think level 3 is better, but I don't have an example to hand.

Kevin Aylward snipped-for-privacy@anasoft.co.uk

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SuperSpice, a very affordable Mixed-Mode Windows Simulator with Schematic Capture, Waveform Display, FFT's and Filter Design.

Reply to
Kevin Aylward

I have now removed this checking in my XSpice engine and posted this updated to my site.

It seems quite useful to allow diodes to be used as capacitors in general, and I don't see any real reason for making an artificial restriction on this. I also removed the checking on EG preventing it from being set to below 0.1.

Kevin Aylward snipped-for-privacy@anasoft.co.uk

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SuperSpice, a very affordable Mixed-Mode Windows Simulator with Schematic Capture, Waveform Display, FFT's and Filter Design.

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Kevin Aylward

Indeed. Essentially, one needs to have a proper BSim3v3 model. Sometimes I kludge one up from a nominal one. The BSim3 is very smooth. It starts with a higher slope then moves into the lesser slope.

Its a little annoying that manufactures don't provide their BSim3 models, as they do have them. They characterise their process to the nth degree.

Kevin Aylward snipped-for-privacy@anasoft.co.uk

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SuperSpice, a very affordable Mixed-Mode Windows Simulator with Schematic Capture, Waveform Display, FFT's and Filter Design.

Reply to
Kevin Aylward

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