differential amplifier poles & zeros

Hi,

I've been trying to optimise the frequency response of a CMOS differential amplifier, but I'm running into difficulty - my first-order hand calculations give completely different values from what I'm getting from simulation, so I don't know which node in my circuit corresponds to which poles.

I was hoping that someone could just run through my thinking and confirm/deny whether I've got the right idea for the first-order analysis.

The circuit in question is here:

formatting link

The first significant pole is at the drain of M3, and consists of the capacitances: Cgs3 + Cdb3 + Cgd1 + Cdb1 + Cgs4 + (1+A)Cgd4, where A=(gm4)(rds4||rds2), ie. miller effect, and the resistance: 1/gm3

And second significant pole is at the drain of M4 and consists of capacitances Cgd4 + Cdb4 + Cgd2 + Cdb2 + (1+A)Cgd5 + Cgs5 (with A = (gm5 || ro)), and resistance (1/gm4)

Finally, a third significant pole is at the drain of M5, consisting of Cl (the load capacitance) + Cdb5, with resistance ((1/gm5) || Rload).

I don't have any numbers to hand right now, but roughly from memory, with the above first-order analysis my values were just wrong - they would predict a pole at say 1Mhz but looking at the pole/zero plots from a simulation, there were poles at 300kHz and 40MHz, but nothing at

1MHz.

Is my theory right? If so, why the large discrepancy? Second order effects? Or have I gone wrong somewhere?

Thanks for any help,

Bill

formatting link

No.

Well, from inspection, and er..uh.. common knowledge of how this stage conventionally works..no the first significant pole is not due to m3. If this stage is designed correctly, there should be large gain from m5's drain to its gate. The main gain is then gm(m1,m2).Xc, where Xc is due to the gate drain capacitace of M5. This is the main main pole-splitter stage. The gate node of mg5 should look aproximatly (to 1st order) as a virtual eartch, i.e, tending to a low value. This means that the gain from m2 gate to its drain is low, hence its miller gain for its cgd is low, just as the other half of the diff pair has low gain. This means that input capacitance is low on both inputs.

M3 is a diode connected load, hence it has a relatively low impedance, making its pole relatively high.

Since m5 forms the main roll off by feedback, its output impedance is also low at HF, which means the effect of load capacitance at m5's drain is minimised.

So, you can see that the miller cap at m5 does a few things. That is why this circuit is so universally used.

Now that the circuit operation has been explained, you should now be able to do the sums.

Kevin Aylward B.Sc. snipped-for-privacy@anasoft.co.uk

formatting link

SuperSpice, a very affordable Mixed-Mode Windows Simulator with Schematic Capture, Waveform Display, FFT's and Filter Design.

"There are none more ignorant and useless,than they that seek answers on their knees, with their eyes closed"