Design impossibility : one NAND from a thousand XOR gates

This should work:

But... it might get a little hot with a H and L input.

Cheers

Wired-AND is not a gate solution.

There was a Fairchild effort called (?) CML (current-mode logic) that was kinda like ECL, but without inversion. So, all the logic was followers, no inverters and only wired-OR. Logic margin dropped at each stage. The way to make it work, is every three or so stages, you had to have a latch or flipflop, which had positive feedback and both polarities of output.

The 'gates' were useful as analog followers, but I never saw any logic systems built of that technology.

Integrated injection logic and majority logic were also interesting, but mainly just footnotes nowadays.

Thanks for that information, now we can all move on from our attempts to do it.

Sylvia.

Well... if the gates were realised with discrete fets, it could be done as one could then connect each gate's 8 inputs (the fets' gates) differently.

NT

Maybe a little. We're working against "impossible."

Why not?

There are still CML parts around, gates and flops and comparators. We use some. NB7V52 is a CML out DFF good to >10 GHz, and only $12.

If A is high and B is low (or vice versa) which one will win?

NAND is a pseudo-idempotent operator (A NAND A = not A) but, by inductive argument, all XOR-derived structures are either idempotent or non-idempotent.

That may be, but what made you even think of this? XOR gates are more transistor intensive than simple NAND or NOR gates. Why would you want to use XOR gates as your primary logic gate?

Rick C.

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It is as promising as, well, promised; it just got taken over by the easier-to-use CMOS.

I've applied IIL principles in a few analog circuits, for example a comparator and level translator with current consumption a fraction of an off-the-shelf gate drive IC.

Tim

Low. The NMOS has about half the resistance of the PMOS.

It's not CMOS though, it's NMOS. The PMOS is only acting as a pull-up resistor, a rather massive one at that (~10mA).

If one restated the proposition as "impossible with CMOS", or "impossible without violating connectivity rules", it would be correct.

Tim

even though it's already been explained how it can be done :)

NT

IIL was said to allow transistors to overlap slightly but I don't remember anything else about it. What principles could you apply to a discreet circuit?

Because it uses/assumes unspecified behavior. In CMOS , outputs-connected defines no valid logic state.

We do that all the time. Besides, you can find curves for the internal fets in a gate.

The nfets will always win, especially at 3.3 volts.

The point is that the specified function is not impossible.

There are a couple other ways to do it. Have a try.

The terms of the specification do not include the special case of a particular hardware implementation; the only fiunction offered was XOR.

The answer responds to a different question than the one posed.

The OP didn't restrict the choice of XOR gate, or specify that ideal XOR gates had to be used. He said that it's impossible to make a NAND function out of XOR gates, so I did it.

Come on, play the game and give it a try. There are several other ways to do it, some even legal according to data sheets.