Well, if I high-passed the (variable with code) height glitches from one DAC and they closely matched the glitches from the other (over different codes), I could subtract the two, and indeed it might be much better than a LPF.
It's an innovative & interesting idea, but the thousands of dollars extra in parts and board area make it a bit less attractive (also it would have to be established that the matching was reasonable between parts). Sounds like st that the chip maker could have done more efficiently.
You mean close the loop around both op-amps with the RC in there? I guess that might need some thought to guarantee stability. The diode leakage shouldn't matter much since it's only got a few mV across it.
What's the advantage of that over driving G1 with a digital signal of, say +10/-5V?
(BTW, and thanks, Phil, one thing that I'd forgotten since the last time I used a dual gate MOSFET it was a little metal can with a spring clip around the leads-- these things are depletion mode, so if you need a _small_ depletion mode MOSFET even with one gate, they're a possibility).
A 4053 has a huge charge injection glitch, which will vary with signal voltage levels and temperature and supply voltages.
Why not?
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John Larkin Highland Technology, Inc
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How is that better than highpass filtering the glitch from the same dac, and subtracting that? I believe I've just described a lowpass filter.
A fast clocked 8-bit DAC could cancel every glitch from the main dac. The lookup table would be many gigabytes, and sort of hard to generate.
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John Larkin Highland Technology, Inc
jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser drivers and controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro acquisition and simulation
2^20-1 bytes = 1Mbyte per time slice, so with 256 time slices,
256Mbytes clocked out every few ns at the transitions. Kind of heroic, but maybe possible. The glitches are currently ~ 10 bits (1000 LSBs) high though, so 8 bits might be a problem (as might be LF noise/drift in the fast converter).
Not clear from your "every few ns" comment :-) ...Jim Thompson
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| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
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I love to cook with wine. Sometimes I even put it in the food.
There are two kinds of closed-loop S/Hs, as JL pointed out--you can run the second stage as a buffer or as an integrator. Either way, you have to do all the frequency compensation in the outer loop due to the two or three lags. Using the integrator method lets you keep the FET's drain near ground, which is nice.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058
hobbs at electrooptical dot net
http://electrooptical.net
That's with your filter. What does it look like, step plus glitch, unfiltered? ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
What I'm trying to say is you CAN'T slew-rate limit it from the digital side, as when you cross one of those major boundaries, you get a BIG glitch, maybe 1/4 scale of the whole DAC range, and lasting for tens to hundreds of ns. Now, some DACs are not bad, and the worst-case glitch is quite reasonable, but some others have horrible glitch magnitude.
I'm sure it varies by the exact DAC construction, but my experience is the glitches are not related to specific codes, but specific transitions. So, if there is a big glitch across the 1/4 scale transition, then ANY transition that crosses the boundary creates a roughly similar glitch. This would be when the N-2 bit changes state. So, my understanding is that eliminating the two states on either side of the transition won't get rid of the glitch. Slowly creeping up on this transition also won't get rid of the glitch. It seems that lacking a DAC which has been designed from the ground up to minimize glitch energy, then some sort of sample/hold circuit would be the only solution that actually works.
(My CMOS DAC's, tucked in my custom ASIC's, sure look better than that :-) ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
You may be onto something here, but slew rate symmetry would be important. I would say an OTA with cap load is more of what you want. gm*C sets the BW, and output stage current sets the slew rate.
Your glitch lasts about a microsecond, and peaks at 40 millivolts. Assume an 8-bit DAC with +-50 mV range. An LSB of the correction DAC is 100 uV, so it can cancel the glitch to within 100 uV, about a 400:1 improvement.
Of course, you need a time sequence of points; say we clock the correction DAC at 64 MHz, so we need a burst of 64 points for 1 usec at each main DAC load, to generate the anti-glitch waveform.
If the lookup table contains every possible code transition of the main DAC, that's a mere 64 * 2^40 bytes of lookup table.
Next, we calculate how long it will take to generate the correction table...
Oh, seems to me that the glitch you posted is a lot bigger than the
1.4 nV-sec glitch impulse on the AD5791 web page sheet.
--
John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
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--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058
hobbs at electrooptical dot net
http://electrooptical.net
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