# Data Acquisition System Calculations

• posted

Hello,

I am new to Data acquisition design so please be patient with me.

Can somebody please confirm the folowing questions about the following chip

1. CS5340 (Audio, analog to digital converter)

CS5340:

a. It has a sampling rate of 192KHz. Am I right, If I say that the maximum input frequency this chip can sample is 96KHz?

b.The chip generates 24 bit values for both left and right inputs at sample rates of 200 kHz per channel. Am I right to say that through put rate will be

24 bits x 200KHz = 4.8 M bits / sec and for two channels it will be 9.6 M bits / sec .

c. Dynamic range is equal to 101 db at 5V? Resolution is 24 bits. I am using the following formula

Dynamic Range = 20 x log ( 2^n - 1 )

But the result is 144 db. How did they get 101 db? And how can I interpret the dynamic range result? Plus what exactly is dynamic range?

d. Am I right, if I calculate the Signal to Noise ratio as follows

S/N = 6.02 X 24 + 1.76 = 146.24 db, Is this a good S/N ratio value? Is it true, higher the DB better the SNR?

e. Total Harmonic Distortion is -94 db . Is it good?

f. The input signal is Neuron Action Potential or Low frequency Potential. So, I was wondering that how many samples can I get with the sampling rate of

192Khz and 96 KHz per cycle?

g. Am I right, If I say that the value of 1 LSB = (5.95) / (2^ 24) =

0.35 micro Volts.

h. can anyone suggest the pin to pin compatiable part for the cirruslogic part number CS5333?

i. I was unable to get the value of offset error voltage of this chip from the data sheet. What is the output offset voltage error?

The CS5340 will be interfaced to intan chip (RHA1016). The data sheet of the Intan chip is as follows

The chip has a multiplexer that has the maximum switching frequency of

500kHz. The data sheet also mentions that the 16 channels can be sampled at

30 ksamples / sec per channel. The ADC is sampling at 192kHz, the max.input signal frequency is 8kHz and be present at all the 16 channels.

I have following questions

1. I want to go through all the sixteen channels at the frequency of
500KHz. So, it will take 16 x 2 (micro seconds) = 32 micro seconds to go through

all 16 channels.Now, Each channel can be sample at 30K samples / sec or equal to 33 micro secs. The ADC will sample at 192 KHz or 5.2 micro secs. SO, Does it

mean that I can take approximately 6 or 7 samples of the input signal per channel at 192kHz. I am unable to deisgn and calculate this part of the system?

Best, John

• posted

Without aliasing. OTOH audio ADCs are pretty highly optimized for audio, so you need to read the data sheet really carefully to make sure there isn't all kinds of junk on the input. Others here can give you better info on that point than I can.

Sure sounds like it.

Because six of those bits were put in by the marketing department and don't do anything useful. See my previous rants in this very boutique, not 'arf a year ago.

You have to be a bit careful here. That formula is for an ideal ADC sampling a sine wave input. The quantization noise for an ideal ADC is

1/sqrt(12) times the LSB size, and the RMS value of a full-scale sine wave is 1/sqrt(8) times full scale (assuming we don't count the half-scale DC offset as signal).

That 1.76 dB is 10 log (12/8).

For a unipolar signal, where full scale DC counts as a signal, you get another 7-1/4 dB from not having to worry about the RMS value of the sine wave, so the formula is 6.02N+9.03 dB.

But again, that's for an ideal ADC, one with exactly equally spaced steps and no noise of its own. Your ADC is nice and quiet--101 dB isn't a bad number at all--but nowhere near 24 bits in real life.

Depends for what. It's certainly inaudible if you're digitizing Metallica. (Rock music has similar statistical characteristics to white noise. Go figure.)

That's what the marketing department would have you believe. In real life it won't sit still to anything like that level, even with the input shorted.

Gigantic.

Cheers

Phil Hobbs

```--
Dr Philip C D Hobbs
Principal```
• posted

Be careful.

1) The reason why there is no dc offset specification is that the adc includes a high-pass filter to remove dc offsets. This may have a bad effect on your signals.

2) You can have a very high sampling rate or a very high dynamic range, but you don't get both at the same time.

3) You will not get the results you expect if you multiplex several inputs to this adc at a high switching frequency. This is because there is a "low group delay" digital filter in there. This means that any particular sample at the output of the adc contains some information from the previous few samples as well as the most recent one. (Not quite correct, as the filter probably looks forward and back in time relative to the current output sample, but the result is equally bad.) If you multiplex quickly the result will be severe crosstalk between channels.

John

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