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Continuing: Preventing mosfet breakdown in boost regulator (LT1961)

Hi,

I have some problems with a boost-regulator using Linears LT1961 which has a built-in FET rated at 35 VDC absolute maximum ratings - it breaks on startup, leaving the FET in near short-circuit (3 ohms..).

The configuration is standard step-up topology with a 10 uH inductor, low-Vf schottky diode, 12-20V input and 28V output. The circuit seems to work fine with 24V output. The output is connected to a 10 uF low- ESR tantalum and a bank of almost 2 mF electrolytes.

I assume this is, like a previous thread here from april discussed, because of voltage overshoot at the switching node - when running at

24V output the overshoot doesn't kill the FET but at 28V I guess it does sometimes. I cannot think of another failure-mode, because the current through the FET is limited internally.

I was wondering what techniques are available to reduce this problem (apart from NOT using 28V of course...). The load is very intermittent (1A but very low duty-cycle) so the average current is only about 30 mA, and there is a large capacitor on the output to even out the current consumption. I was thinking of a simple series resistor at Vin or in series with the inductor but if the problem really is caused by parasitic inductance in the package leads etc this wouldn't help right ?

Another theory I had was that the rush of current at power-on, which goes straight through the inductor and diode onto the (large) output capacitor bank, could cause some breaking. I guess this rush could be alleviated at least by increasing the source resistance at Vin.

I tried contacting Linear about the failure-modes of the internal FET, but got no reply, FWIW.

Best regards, Bjorn W

> Hello: >> I am designing a boost converter, and I am uncertain whether I need to >> take specific measures (and which) to protect the main switch MOSFET >> from the drain-source voltage breakdown. The fet is incorporated in >> the switcher IC, and has the maximum voltage rating of 60V. I want the >> converter's output voltage about 55V. Now, if one takes into account >> the parasitic inductance of the PCB tracks and of the switcher's >> package wires, one would conclude that high-voltage (albeit very >> short) spikes, well above 60V, would be produced across the fet's >> drain-source at switch-off. Even if I could somehow clamp the D-S >> voltage at the switcher's connection to the PCB board, there would >> still be considerable spikes due to the package's own wires (it is a >> TO220-5). >> Can someone help and tell whether I should bother about these spikes, >> and if yes - to which extent? Many thanks! >> -- A >Put a tap in the inductor not far from the output. This will reduce the >voltage swing on the MOSFET, but increase the current slightly. Bear in mind >that the breakdown voltage often has a negative temperature coefficient. >Graham H

Actually Vds limits for discrete mosfets increase with higher temperature but there are very few app environments that can benefit from this feature. Discrete mosfet voltage breakdown is not catastrophic, only energy-limited (as per TVS-characterized zeners) and moisy. The self-heating characteristic of this breakdown limit can even be self-regulating at really low temperatures. Integrated mos structures may show the limit characteristics of the host structure, however, where breakdown behavior is not so predictable. By reducing layout loop area, adding current-snubbing and using rectifiers with low forward overvoltage (schottkys), you should be able to approach paper limits in boost converters, if transient response (start-up and transient output voltage overshoot) is well-controlled. Larger than nominal output capacitance may help. Some power integrated circuits display a odd behavior in the presence of a range of dv/dt or di/dt values - you should make enquiries with the device mfr about any unexplained behavior. There may be a simple empirical solution, whether or not the mechanism is fully understood, or whether an explanation is forthcoming. RL

Reply to
BW
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You could add a 'snubber' circuit to the inductor to dampen any oscillation (small resistor plus cap in series). However the schottky diode should clamp this voltage. I suspect that the large output capacitance might be causing loop stability problems though, and as you say might cause inrush startup problems although I fully expect the chip to be able to deal with that.

I would recomment you getting LTSpiceIV, which is Linear's free Spice simulation packege, and simulating your circuit with the output capacitance you've got. This is a very easy to use SPICE simulator (actually general purpose, you can simulate other things with it too). You might spot something odd in the behaviour.

Mark.

Reply to
markp

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Hi Mark,

yes I have simulated everything in LTspice both before my board-design and now after.. I see nothing strange, except for the inrush current of several amps in the first ms or so (this is depending on the power supply resistance which is unknown though). When the circuit has reached its operating voltage, it seems to respond well to the transient load (also simulated as a pulsed current on the output).

The idea with the snubber might work, it's kind of annoying that it's so difficult to actually measure the values in a live switcher circuit..

The schottky diode will not clamp any oscillation / overswing if the ESR of the output caps is so low that the oscillations actually contributes to overcharging them, right? Then both the switch node AND the output node will land at a too high voltage, regardless of feedback stability.

If you want to see the circuit, here is the .asc which you can load in LTspice:

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The points I checked was the Vin, Vout, L1 current and switch current and the switch node voltage. The latter never exceeds 35V even transiently in the simulation.

Now, the simulation doesn't include parasitic stuff, and the ESR for the caps is not know for the electrolytes (Panasonic EEEFK1V221GP

220UF/35V) so it's not 100% accurate and furthermore I'm not sure you can actually break a FET in a spice-simulation? :)

I guess I'll have to go back to using the circuit at 24V, it's just annoying that I don't know exactly why it breaks.. it always feels better knowing it.

Best regards, Bjorn W

Reply to
BW

You say you have a very intermittent load. Did you check that your output is'nt climbing and exceeding Vds. Some controllers have a burst mode when the output goes below a set point minimum so the output won't climb. I don't know if the LT device you are using has this feature or what the minimum duty cycle is.

Did you check the Vds?

You could try and increase the inductance and decrease the capacitance. For 30mA output current I get about 200uH inductance for CCM?

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If you're worried about inrush saturating your inductor at start up add a schottkey from input to output. The schottkey conducts until the output is more positive by about 0.3V then the input.

But the best way is to put a probe across DS and see if it's exceeding the max by either an inductively generated transient or your output is climbing because of such an intermittent load.

Reply to
Hammy

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You say there are 'several amps' during initial startup conditions? Does your inductor saturate under those conditions (i.e. does it violate the max peak current)? It could be that the simulation model of the inductor doesn't model the saturation behaviour. What will happen when the inductor saturates is it turns into a piece of wire, and the current ramps right up possibly blowing your FET.

Mark.

Reply to
markp

Have you tried any of the suggestions offered in response to the April posting?

Can you post a schematic/layout image (abse or elsewhere)?

RL

Reply to
legg

There is another possibility that any high edge rate and high voltage oscillation on the inductor is coupling into the gate via the parasitic drain to gate capacitance, in which case a snubber circuit should fix it.

Mark.

Reply to
markp

What inductor are you using? Part number or construction.

RL

Reply to
legg

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Hi,

No, I just discovered this thread today.. I will try to measure on one of the working boards and see if the run-time switch voltages are behaving badly. I don't have much hope for this though, the probe disturbs the measurement I think.

Yes, I put them here:

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And the previous LTspice schematic:

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The switch node is as small as I can get it almost, and the current loop from L1 through D1 to C1 back to GND is short as well, likewise the C4-L1-U1 loop.

There is a GND plane just below.

The values for the loop compensation filter C2 C3 R5 are from the LT1961 datasheet. C21, across the feedback node, I forgot that in the LTspice schematic but I inserted it and re-ran with no particular difference.

The strange thing is that I have two boards configured (using other values of R1+R35) for 27.2V operation which works fine, I have 4 broken boards configured for 28V, and then I have one board at 26V which first worked then broke :) I assume this can be accounted for due to part variations though. I have more boards at 24V which never have failed though, so there definitely is a threshold for the "dragons"...

Best regards, /Bjorn W

Reply to
BW

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Hmm, perhaps, but wouldn't the FET current limit circuit have time to shut it down before this ?

The inductor is TDK VLCF5020T-100M1R1-1 (10uH, 1.13A) but the datasheet isn't very useful, the 1.13A rating is not the saturation current at least.. :( I guess I could play with different inductors if I find some that fit the same footprint.

Best regards, Bjorn W

Reply to
BW

Here's a theory: This is a boost regulator, so during the time the output voltage is somewhat lower than the input voltage the inductor, diode and output capacitors are in series. I've just done some simulation, and the current ramps up to 14A or so in 30us, then gradually reduces over about

10ms to something sensible (ideal inductor). The FET is at some stage going to turn on because the output voltage is below that which is demanded and the FET was initially off, but when it does so the current is diverted through the FET from the inductor for the time needed for the current limiting feedback circuit to turn the FET back off. The max current the FET will sink here will be determined by the point at which the inductor saturates. It might be that having such a large ouput capacitance has meant that the FET spends much more time sinking very high current spikes. If this is the cause then the rise time of your power supply to this might also have an effect.

Mark.

Reply to
markp

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Yes, this occured to me when I looked over the simulation as well.. this stuff with very transient high currents, it's difficult to know how much it hurts a component if the manufacturer does not specify it or answers tech-support :)

But yes, when plotting the switch-current in the LT1961 model, assuming it is correct in this respect, it does look as if it doesn't have time to shut it down before the super-current hits it and then it's hit by these high spikes for a number of ms.

You would expect the Schottky to take away some of the current, but the low RDSon of the built-in FET of 200 mOhms competes favourably with the ESR of the output caps I guess (this much is simulated well I expect).

I don't know much of inductor saturation physics so I don't know how that factors in. Even without saturation, having 10 amps through the inductor would be even worse because that's a lot of magnetic field energy that wants to keep coming out so to speak.

I guess anything that limits the current during startup would fix at least this part of the problem.

Anyway.. this behaviour at start-up can't be unique for my setup. I'd expect the switch regulator designers to know about these issues. Perhaps the LT1961 is simply too sensitive in this regards..

/Bjorn

Reply to
BW

From another recent posting on this news group re schottkys at high current, the large surge in the 1N5819 may add to the switch stress, as reverse current is not even limited by the saturated inductance of the coil:

Larkin - quote "Some schottky diodes have P-N guard rings for some semiconductor-ishreason. At high forward currents, when the schottly drop gets to abount 0.6 volts or so, you can forward bias the PN rings and see reverse recovery from that. So don't push schottky power diodes too hard, or at least experiment to see if this is going to be a problem."

The 1N5819 was one of the first guard-ring protected power devices.

The inductance of the choke is 30% at it's rating. If typical Hanna curbes are anything to go by, at 10x current rating you might expect

3% remaining.

Note that the switch in the 1961 is a bipolar transistor. This sets a limit on possible peak current as a function of device internal beta, but also introduces SOA and switching speed considerations.

As the 1951 is normally expected to deal with switching spikes associated with schottky rectifier capacitance, there may be an unspecified blanking period present in the internal sensor that results in a minimum switch 'on' period, regardless of switch current.

The spice simulation shows 12A peak currents in the ground pin during the turn-on current surge, of 15nSec duration. This probably doesn't occur in real life, as it is unlikely to be physically possible either of the bipolar switch or the other hardware present. It does suggest, however, that the chip is the only thing present that could prevent damage, if it were capable of doing so.

RL

Reply to
legg

One thing that might help. You currently have the SHDN# pin connected via a potential divider to the input voltage. As it's a boost regulator, the output will always rise up to the input voltage minus a schottky diode drop anyway, so you could take your voltage for that from the output voltage instead. This would delay the turn on until the current through the inductor dies right down. In fact I modified your simulation file and it does seem to work (R4 voltage now comes from the output voltage of the junction of D1 and R1 rather than Vin, and changed R5 to 22k).

However you're still left with the inrush current problem of 14A or so (maybe higher, as the inductor is possibly going to saturate before then).

There is another option for you, and that is to abandon the LT1961 and use a buck-boost regulator instead, e.g. LTC3533. This uses a single inductor for buck/boost mode, but that inductor is effectively isolated from the input supply by FETs and has a 700mA short circuit foldback current limit on it, which the datasheet suggests is used for 'startup conditions' and short circuits. Note of warning though, the Spice model for this is *broken*, it does not simulate the short circuit foldback properly - if you simulate this with the output tied to ground or a very low resistor you'll see that the current ramps up to it's normal max of 7A contrary to what the datasheet says. Linear are aware of this, I've had confirmation that the model is wrong via email.

Mark.

Reply to
markp

Oh forgot, that is a low voltage regulator of 5.5V max output voltage :(. You get the idea though, find a buck-boost regulator with short circuit current limit.

Reply to
markp

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Good idea - I tried this but did a modification - because I have to support 12-24V input, I'd get the same problem at 24V input if I simply connect the SHDN divider to Vout and make it start up at 10V. So I figured, keep it at Vin but just put a 1 uF cap (or more) in parallel with R5, effectively delaying the startup of the regulator for as long as needed.

Easy fix for my current boards as well..

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Yes. However, as long as the inrush doesn't by itself generate potentials at the switch-node of more than the maximum rated voltage, this is "just" a problem for the inductor and the caps, and they seem to have survived all my previous experiments.

I'llt try with the delayed startup and see if I break more LT1961's and report back ;)

(Yes, for the next design I will probably chose a boost-regulator with a stand-alone switch FET which I can dimension anyway I want... any recommendations ?)

Best regards, Bjorn W

Reply to
BW

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Just for future reference in case anyone runs into the same problems, I'll post some results I got after some more testing below.

First recap: the Linear LT1961 in a boost topology designed for 12-24V input, 28V output at a low current (20-30 mA average), breaks the LT1961 in various ways at startup (two failure modes - either the integrated switch becomes a short circuit, or it becomes completely disconnected, non-operable). The LT1961 is rated for 35V absolute maximum rating on the output side and should work for this according to the datasheet.

So I ordered more of the LT1961 and changed them on the broken boards, with various (systematic) modifications of the desired output voltage,

24-28V, I also tried the above fix with the delayed \\SHDN release, to avoid starting the switcher in the middle of the inrush current.

The result:

  1. The SHDN-delay didn't change anything.

  1. All the 25-26V configurations worked (without further modifications), I tried cold-starting them many many times

  2. Some of the 27V configurations worked

  1. Some of the 27V configurations broke

  2. All the 28V configurations I tested broke (this was the old result)

  1. I measured the startup 50 ms with an oscilloscope at Vin and over the output cap, and actually captured the breakdown events. What happens is that the output voltage never in any case overshot the desired value - it rose monotonically in a nice way. Still, there is a very short rush of current (visible as a 100 uS dip in the Vin supply)

1-2 times occuring just when the output hits the programmed level (about 25 ms after the LT1961 enables itself), after which Vin decays exponentially due to the created short-circuit. Very interesting! (and tedious since I had to hot-air replace a MSOP-8 part with a hidden gnd pad each time...)

From the above I'm not sure I can draw any conclusions but it seems that there is something wrong with the LT1961, at least the datasheet is not accurate on its performance unfortunately. I will definitely have to change it to another part in the next revision - probably something with a stand-alone transistor so I can dimension it generously. For now I will have to do with 25-26V on the current prototypes. I assume the reason some 27V configurations worked is because of unit variations.

The failure modes (shorted or open transistor) probably occurs because either the connection burns up or the substrate burns up..

One possibly interesting effect I saw in the LTspiceIV simulation of the LT1961 is that just when it reaches the desired output level, and before it stops doing switch cycles, the switcher goes crazy - the current into the SW pin oscillates sinusoidally just after it has closed in the switch cycle. I hope this is a bug in the simulation. I guess I will never know unless there is a DC/DC Linear guy reading this ;)

Best regards, Bjorn W

Reply to
BW

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Now i am curious. That shot of oscillation interests me. What is the frequency? Did you say it shows up in both the simulation and the real product? Does the real product oscillate at a reasonably close frequency to the simulation?

--=20 Transmitted with recycled bits. Damnly my frank, I don't give a dear

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Reply to
JosephKK

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