1. Home
  2. Electronics Design
  3. Consistent algorithm for PCB SMD lands?

Consistent algorithm for PCB SMD lands?

Greetings:

What, is this the holy grail or something? I try to design a consistent algorithm on land sizing and placement, only to find it leads to problems with the next package I try.

For instance, I did an MSOP-8 on a 25um grid:

I set the land outer boundary to 2.900mm based on max origin-to-lead dim of 2.525mm plus 2/3 of the nominal foot length of 0.56mm.

Next I set the land inner boundary to 1.625mm based on min origin-to-lead dim of 2.375mm minus 4/3 of nominal foot length of 0.56mm.

Land width 0.45mm equal to max lead width of 0.40mm (rounded up Vishay's

0.38mm) plus 0.025mm on each side.

There is 0.2mm (approx. 0.008") spacing between lands.

Ok, so I get a land size of 1.275mm x 0.45mm

The approach is aimed at producing a decent proportionality of land extending beyond the tip of the lead and also under the foot (toward the part's body) of about 2/3 outer, and 1/3 inner, while also accounting for tolerances in the package manufacturing.

Oh then there is the question of how to draw the package outline for the silkscreen. For this one I opted to put the outer edge of the 0.2032mm (0.008" is the minimum allowed by my PCB fabricator) silkscreen line at the point representing the max dimensional tolerance of the body. Fortunately, this cleared both the land and its solder mask relief.

Applying the same method to a SOIC package, I get into trouble. The lands extend a bit too far out than is really necessary, and they go under the package too far, getting into the silkscreen. Applying arbitrary adjustments gets the job done, but breaks the consistency.

Basically, with a consitent algorithm, I could make SMD packages quickly, without fussing for hours over whether to bump things a little this way or that. But I haven't been able to conjure a working algorithm.

What do you folks do? Has anyone else obsessed over this?

Good day!

--
_____________________
Christopher R. Carlen
crobc@bogus-remove-me.sbcglobal.net
SuSE 9.1 Linux 2.6.5
Reply to
Chris Carlen
Loading thread data ...

Hoo, yeah... many, many hours. :-)

FYI, IPC guidelines vary depending even on the soldering method being used...

Here are the formulas we use:

Pad length = Max_Foot_Length + (Package_max_variance_toe_to_toe * 0.5) + 0.25mm for toe fillet. (Generally leaves room for plenty of fillet at the toe, and under the heel where it bends up from the foot.)

Pad width = Max_Foot_Width, rounded up to an increment of 0.05mm (Fine-pitch like TSSOP don't have room for side fillets; TQFP-64 could easily handle side fillet.)

Placement silkscreen = max package size, unless its outer edge gets within 0.2mm from a pad (in which case it'll overprint or get clipped during pre-processing). Actual package max size is also added to the documentation layer so it shows in the layout, but not on the board.

So far, this approach works pretty well, without much fine-tuning required. YMMV, and no doubt there'll be opinions on it. (IIRC, these side and toe fillets are not IPC spec, but we're also hand soldering.)

Cheers, Richard

Reply to
Richard H.

On Sun, 22 May 2005 18:37:26 -0700, Chris Carlen wroth:

Almost everything done at my workplace is a prototype and must be hand soldered. Even the 0402 parts. Thankfully, we haven't gone to BGAs... yet. Hand soldered footprints often need to be just a little different from ones intended for solder paste and reflow. Few boards have, or need, component silkscreens, so that helps. But I still have to adjust footprints to fit. The Protel library footprints are not very consistant. Sometimes it takes a couple of iterations to get things managable. But the bright side is that once I'm happy with a footprint, I seldom need to change it.

Now, if I could just convince my fellow board layout guy to quit dropping vias through the middle of bypass cap ground pads to ground planes and then expecting ME to solder his abortions, I'd be in high clover.

Jim

Reply to
James Meyer

Stick around - you might be pleasantly surprised. :-)

... If it were me, I'd just take apart a remote control or cell phone and measure the danged things. Somebody has already done all of this homework, so why not just copy the way the successful ones are already doing it? :-)

Or, maybe talk to your pick-n-place folks.

Good Luck! Rich

Reply to
Rich Grise

good question. I have PDFs of a couple of IPC standards, which cover a lot of parts. Some parts however are not covered, and often the manufacturer doesnt give any recommendations either :(

I set a silk-screen (and mech layer) outline (on a 0.005" grid) sized to ensure I meet the relevant IPC placement rules (eg take into account shadowing effects for reflow...). I nominally use 0.02" out from the pads, but always check every new footprint (there are a variety of excuses for building pcbs with components that collide, none of which are flattering)

When I lay out a PCB, I place my parts such that the mech outlines are all touching (hence the 0.005" grid). The spacing is such that I can run (0.008") traces wherever I need to (say between adjacent 0603 parts). Many of my layouts are actually packed this close, but sometimes vias make space things out more.

Cheers Terry

Reply to
Terry Given

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.