CircuitMaker Step Time puzzle

Any CircuitMaker users have any thoughts on this puzzle please? I've been running the simple CMOS astable at

I know the 1k resistor is far too low (330k would be good), but that's not the point of my post.

At certain settings of Step Time (= Max Step), the waveform is not identical from one cycle to the next.

One such critical value is 1 ms. With that chosen, successive Lows differ significantly in length. I've illustrated the 1 ms result here:

You can clearly see the variation in successive cycles. I measured about 4.3 ms versus 5.4 ms, while the Highs remain identical at 5.0 ms.

So, depending on which choice of cycle I happen to make, I get a different frequency: 97 Hz versus 104 Hz. Yet at 990 us (i.e. only a tiny difference), I get a *consistent* waveform and hence a consistent frequency measurement (97 Hz). But at Step = 100 us, I also get a consistent frequency, but now it's 114 Hz.

Any insights appreciated please.

Terry,

The problem is basically two fold. CircuitMaker doesn't implement predictors in its digital logic and it also doesn't use tolerances specificed in time. You can only address the issue by stipulating a smaller timestep which usually will compute the same circuit more accurately.

LTspice can use both prediction and temporal tolerances, but only temporal tolerances are readily available to most users. Below is a schematic that illustrates the use of temporal tolerances to the behavioral gates.

--Mike

--- snip.asc --- Version 4 SHEET 1 880 680 WIRE 32 208 48 208 WIRE 48 208 48 224 WIRE 48 224 96 224 WIRE -32 240 -64 240 WIRE -64 240 -64 48 WIRE -64 48 -16 48 WIRE 224 48 304 48 WIRE 48 48 96 48 WIRE 304 48 304 192 WIRE 304 224 240 224 WIRE 240 192 304 192 WIRE 304 192 304 224 WIRE 96 48 96 96 WIRE 96 176 96 224 WIRE 96 224 176 224 WIRE 96 48 144 48 WIRE 304 224 304 240 WIRE 304 304 304 336 WIRE 48 224 48 240 WIRE 48 240 32 240 FLAG 304 336 0 SYMBOL digitalor 0 160 M0 WINDOW 0 -42 28 Right 0 WINDOW 3 5 113 Left 0 WINDOW 123 5 141 Left 0 WINDOW 39 5 169 Left 0 WINDOW 40 5 197 Left 0 SYMATTR InstName A1 SYMATTR Value Td=50n SYMATTR Value2 Trise=50n SYMATTR SpiceLine tripdt=1n SYMATTR SpiceLine2 Vhigh=10 SYMBOL res 240 32 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R1 SYMATTR Value 1K SYMBOL res 80 192 M180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R2 SYMATTR Value 330K SYMBOL cap 48 32 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName C1 SYMATTR Value 82n SYMBOL cap 288 240 R0 SYMATTR InstName C2 SYMATTR Value 10p SYMBOL digitalor 208 144 M0 WINDOW 0 -42 27 Right 0 WINDOW 3 3 107 Left 0 WINDOW 123 -8 137 Left 0 WINDOW 39 0 163 Left 0 WINDOW 40 -1 195 Left 0 SYMATTR InstName A2 SYMATTR Value Td=50n SYMATTR Value2 Trise=50n SYMATTR SpiceLine tripdt=1n SYMATTR SpiceLine2 Vhigh=10 TEXT 296 360 Left 0 !.tran 10 uic

Thanks Mike. I'll play with that tomorrow.

Yes, that was one of the points I was making. Obviously 97 and 114 can't both be accurate!

This is an astable running at about 100 Hz, i.e a period of 10 ms. Strangely, if I let CM use defaults, it sets Stop Time = 5.000uS and Step Time = 20.00nS. Not a useful display! BTW, it always uses that same ratio of 50:1. When I set manually, as I did in these tests, I usually choose 500 or 1000. Your reply seems to reinforce my intuition that 'shorter is better', So why does CM (and several other Spice programs I've used) default to 50? And any idea why it comes up with such an absurd default setting for a circuit with an RC of 33k/82nF?

Thanks, I agree 1 ms was too crude. I think I must have been 'comfortable' with it on the grounds that at 1000, the ratio 1s/1ms was so much higher than CM's 50! And lost sight of the underlying circuit. Using 1us prompted me to revise the Stop Time down from 1s to

I'd previously followed similar practice. Thanks for prompting me to realise I'd lapsed, fro reasons above.

Do you think there's something of that sort happening here, and causing CM to come up with a Stop time of 5us?

Dunno about that, but the only time step settable in CircuitMaker is the algorithm period. If you set it coarse enough, you can get a parallel L-C to oscillate, or even a parallel R-C.

I think the Spice interval is adaptive; you can set the min and max time step, and it gravitates towards the max when not a lot is going on in the circuit.

My old favorite DOS simulator, ECA, wasn't Spice-based but worked the same way, only not adaptive. It was a lot better than Spice in many ways.

Simulators are interesting in that you really have to understand the circuit and critically evaluate the results or risk believing nonsense.

John

Maybe things have changed, but the original SPICE timestep specification had to do with times at which the simulation results are stored for output display and NOT the mathematical time increment size required for convergence of the integration algorithms which was derived from error tolerance parameters.

Fred,

The academic codes have two time step sizes to specify. The first one is as you describe. It was required in the old days because the outputs were ASCII plots and you had to tell it how often to print a line. The timestep doesn't do much these days and even less in a program like LTspice since it stores data as compressed vector graphics independent of any regular time step size.

John would be talking about the other timestep, the fourth number on the .tran command, which is a stipulation of the maximum timestep size over which the circuit reactances can be integrated.

--Mike