Choosing by pass and decoupling capacitor for an optocoupler

Hi all,

I am trying to figure out the size or capacitance value for the following chip ( IL- 715 ),

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I know that I can use the following formula to find the capacitor

C = ( I x N x t ) / V

Where, C = Capacitance I = Current needed to switch output from low to high N = number of outputs t = time required for the capacitor to charge V = allowable voltage drop in Vcc.

The problem is that I can not find the current needed to switch output from low to high and also the drop in Vcc in the data sheet. Can any body give some suggestions!! Is there another practical method to calculate capacitance value?

I am planning to use all four channels of the IL-715. The signals are

30MHz frequency clock signals.

Regards,

John

Reply to
john
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Use a 0.33 uF, 0805 or 0603 cap per side, per chip. That will be plenty.

John

Reply to
John Larkin

Yikes! To use this formula means you need to know more than you could ever hope to know about your power supply lines and the part over temperature and unit to unit variations.

You're trying to supply a low impedance power source to the part, especially when switching. The job of the decoupling capacitors is to handle the current spike on the power supply lines during transitions. You must think about the layout of the parts as trace length on your bypass capacitors will increase inductance which increases the impedance at higher frequencies.

For this sort of thing, you can use basic rule of thumb design guidelines - use 10nF caps real close to the power supply pins (minimal loop length between the power and ground pins). One or two

100nF caps nearby is also a good thing. Somewhere on the board, you should have some bulk capacitance in the 100s of uF which takes care of the lower frequency garbage. The bulk C is for all your circuitry.

It's also good to have a solid ground plane and power plane closely spaced. The planes will form a good quality capacitor which aids in decoupling. At least a solid ground plane. With power and gnd planes, you could probably get by with just the 100nF caps close to the power supply pins and ditch the 10nF parts.

After you lay out your circuit, monitor the power supply pins on your parts and see if the noise is acceptable (usually less than 50mVpp). Be sure to use proper oscilloscope probe grounding procedures for high speed signals or you will end up with a higher noise reading. Proper grounding technique: don't use the dangly ground lead on your probe, connect the probe ground ring to the board system ground. You can use a small screw driver to bridge the ground ring to system ground.

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Mark
Reply to
qrk

Why that much? The spec says 47nF low-ESR per Vdd.

Reply to
DJ Delorie

Why not? If the caps are much bigger, they start to cost more. Otherwise, the bigger the better, since ESR and ESL don't change much with C. But sure, 47n will work, too. It doesn't matter much.

We buy 0.33's by the reel, 3000 at a time, and sort of spray them everywhere... over 100,000 so far.

John

Reply to
John Larkin

Hi,

I know the thumb rules etc. But I am looking for some formula or mathematical solution to this problem. I know 47nF valus is given in the data sheet. But how did they come up with that?

I read the following note from texas instrument , Please take a look at it,

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The note has the formula which I mention in my post. I am unable to find the switching current value.

Regards, John

Reply to
john

When a digital IC switches, it (or most of them) draw a brief Vcc current spike. The spike is sometimes characterized as a packet of charge Qs, or as a "switching capacitance", where Qs = Cs * Vcc.

For a single switching event, the bypass cap should be much greater than Cs, with the result being that the spike can't change the voltage across the cap very much, and Vcc stays stiff. The Cs values are usually in the picofarads for typical small CMOS parts, but can get higher for bigger stuff, FPGAs or mosfet gate drivers, whatever.

For very fast logic, the parasitics of the bypass cap, especially ESL (equivalent series inductance, of the cap and its leads) get to be the big worry. ESL for, say, an 0603 cap depends on the geometry and not much on the C value, so it's fine to use the biggest cap that's still cheap. ESL is reduced by using multiple caps and especially by using close-spaced power and ground planes or pours on a multilayer board.

You really don't, as a practical matter, need a lot more theory than that. There's no simple formula here. Everybody has different bypassing theories because they all generally work. If engineers do anything wrong, it's generally that they use too much "theory" and too many caps. I know one guy who doesn't use bypass caps at all, and his stuff works too.

If the switching frequency is variable (like a uP that switches differently and varies its Icc as it executes various code) then you should ensure that the power supply remains stiff at lower frequencies too.

John

Reply to
John Larkin

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