Can somebody take a look at this circuit for me?

I'd add a zener s-g on the upper fet to keep from blowing out the gate under various weird conditions.

The loop may be unstable, and needs analysis. A resistor in series with C1 might wind up being needed.

Otherwise, should work.

John

Reply to
John Larkin
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One problem with power MOSFETs is that they have a nasty tendency to self-oscillation at a few hundred MHz, which can often be tamed by a low value resistor (10R to 100R) in series with the gate - R2 probably does this job for U1, but you might want to try adding such a resistor at U2.

As John Larkin has pointed out, the delays around the feedback loop are fairly high, and the stability could be a worry.

The 8pF input capacitance of the op amp with 100M at R3 gives an

800usec RC delay around the outer feedback loop, which R5/C1 seems to be intended to take care of, but I too have found myself putting a resistor in series with C1 in similar situations.

Bill Sloman, Nijmegen

Reply to
bill.sloman

Hi - can anybody here tell me if this circuit will work? The idea is for it to take an input of 0-10V DC at point VIN and output 100 times that at VOUT. This is the circuit, drawn up with Cadsoft Eagle:

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Op-Amp is a TI TLC2274:

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(beware - fairly large datasheet)

Mosfets are both Internation Recifier IRFBG20:

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Before I go any further - I should say that this is pretty much 100% John Field's design (with some minor modifications by me in the choice of a higher voltage FET and a higher input voltage) - but I figure I've pestered him enough so I should post it here instead.

I tried building this circuit today and I ended up frying the op-amp, and possibly one of the FETs. I'm not exactly sure how that happened, possibly a short, though my wiring looks fine to me. I'm not worried about it as I ordered up plenty of both the fets and the op-amps though.

Anyways - what do you all think?

-Michael J. Noone

PS I tried to test this circuit out with LTSpice - but I was unsuccessful. Can somebody tell me what I'm doing wrong? This is my LTSpice file:

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and this file needs to be in the same directory:
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Reply to
Michael Noone

Are you really sure that your active load ( U$2 ) is meant to be configured like that ?

Oh - it's just the way you drew it that's confusing. How *do* you generate such odd component references btw ?

It's quite likely unstable. Try using sensible feedback Rs for starters like 1M ( watch the wattage ) and 1k

You can protect the op-amp by adding clamp diodes to its supply rails btw.

Graham

Reply to
Pooh Bear

it

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pestered

possibly

I would say this would be essential, without it the top mosfet would undoubdetly blow as soon as the botom mosfet turns on hard as the top gate will be pulled down to 0v but there is nothing to pul the output down so the full output voltage wil apear acros the gate, also any leakage on the top mosfet wil have no where to go and try to go through the gate.

This looks like quite a comon output configuration but it is mising that diode, wich provides a path for the botom mosfet to pull the putput low.

yeah, wil be needed if the op amp isnt unity gain stable.

id add a zener on the gate of the botom mosfet too to be safe, if the output falls instantaneously the gate may well be puled negative by more than 20v by the gate drain capacitance, as the 1k gate resistor probably wont stop this but a zener will.

Colin.

Reply to
colin

Sorry, I meant connect a zener from the source to the gate of the top fet. Allow the gate to go, say, a maximum of +10 volts above the source. The zener will also keep the gate from going more than about

0.6 negative relative to the source.

John

Reply to
John Larkin

A TVS *is* a zener, usually a big, slow (as in high capacitance) one.

John

Reply to
John Larkin

My guess. U2 Gate and Source should have a TVS (transient Voltage Suppresser) diode rated for just at or below the max gate voltage be gate voltage. also the resistor values on the + input seem kind of high, i would think that internal capacitance of the Op-amp + input may cause some time delay related problems in biasing! in that case, i would use a lower divider network values. 10k , 100K looks good.

P.S. zener diodes can also be used for the gate suppression idea how ever, they do not offer the speed of response like a TVS does.

Reply to
Jamie

Pooh Bear wrote in news: snipped-for-privacy@hotmail.com:

What do you mean odd component references? The names are all auto generated by Eagle.

The size of the resistors used in the voltage divider circuit will affect the performance of the circuit? I chose those high values as I figured they'd be fairly easy to obtain and not consume much power - but I definitely can change to a smaller set of resistors if needed.

Can you elaborate on this? I'm afraid I'm not familiar with the term "clamp diode" - and googling it turned up many results relating to things like relays, (where I am familiar with the use of diodes to dissipate the inductive energy stored in the coil).

Thanks!

-Michael

Reply to
Michael Noone

snipped-for-privacy@ieee.org wrote in news: snipped-for-privacy@o13g2000cwo.googlegroups.com:

I forgot to mention this in my first post - but this circuit will not be run at a very high speed. It will be switched to a voltage, and then held there for a second or so. In testing a similar circuit I found it took about 30ms to stabilize, which is ok, but if I could get it to stabilize faster than that that would be ideal. Also, I'm not sure how this circuit will handle varying loads. If it matters - current through the output will be very low, probabaly in the micro amp range. So with that said - do you think I still need a resistor for U2?

Right - is there any way to improve upon this? I'm afraid I'm not particuarly experienced when it comes to FET amplifier design.

Would a different op-amp with a lower input capacitance improve upon this? I am not stuck to the TLC2274 in any way.

Thanks!

Michael Noone

Reply to
Michael Noone

John Larkin wrote in news: snipped-for-privacy@4ax.com:

Hi John - what exactly is a Zener s-g? I've never seen the term s-g before, and I was unable to find anything on google.

Thanks,

-Michael

Reply to
Michael Noone

"Michael Noone" schreef in bericht news:Xns9654A698F3Amnooneuiucedu127001@216.148.227.77...

How you use the circuit doesn't affect U2's tendency to self-oscillation. If the gain around the relevant loop is high enough, Johnson noise will be enough to start the oscillation. We had enough trouble with power FETs going into self-oscillation at Cambridge Instruments that a 10R resistor in series with the gate was always designed in - if we had the pads on the printed circuit it was easy to swap in a higher value resistpr if necessary.

The nasty part of the problem was that self-oscillation at over 100MHz wasn't always visible on cheap portable oscilliscopes, so the service engineers could get thoroughly puzzled.

It isn't a problem that is specific to FET amplifiers - all negative feedback amplifiers can oscillate if there is too much delay around the feedback loop. The trick is to make sure that the loop gain (plotted against frequency) falls to less than one before the phase shift has reached 180 degrees.

The Texas Instrument MOSFET input op amps do have a relatively high input capacitance, and I got caught years ago by the TLC2201, back when TI didn't include that bit of information in the data sheet, but 8pF isn't much higher than the 2-3pF you see with most op amps.

Lowering R3 and R4 would be easier than finding a new op amp, but all you really need to do is make sure that the negative feedback around the op amp isn't greater than one at frequencies where the phase shift through the feedback paths exceeds 180 degrees.

Any decent electronics text covers this subject - Horowitz and (Win) Hill's "The Art of Electronics" has a couple of pages on the subject (chapter 4 - sections 4.33. 4.34 and 4.35 are well worth reading).

Bill Sloman, Nijmegen

Reply to
Bill Sloman

Michael Noone said

Maybe I'm missing something here?

Shouldn't the upper FET be a PFET with the 1Meg from Gate to Source?

Additionally, I'd think you'd want to provide the 1/1000 feedback to the negative input of the OPAMP.... with the positive input getting the command voltage.

Otherwise, can someone give me quick verbal circuit description?

Reply to
Homer.Simpson

Homer.Simpson said

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Here's a scaled down version:

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Reply to
Homer.Simpson

Homer.Simpson said

This one's passed validation and is ready for mass production:

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Just don't ship it anywhere near me. Are you really messing with 1KV?

Reply to
Homer.Simpson

You would put the diode between the pin you want to protect, and the positive supply rail in such a way that it is normally reverse biased. Only if the voltage at the protected pin goes above the supply Voltage does the diode experience forward bias. Is that clear enough?

Something like this: (Use courier or other fixed-width font for ASCII art schematic)

VCC | +-----+ | | | --- clamp | / \\ diode |\\ | ----- | \\| | | \\ | | \\----+------> To dangerous load | / | | / --- clamp | /| / \\ diode |/ | ----- | | +-----+ | GND

In your circuit, you might want to protect the non-inverting input pin and or the output pin.

I agree with the others who say that the upper FET definitely needs Zener protection. Might as well add it for the lower one, too. You would use maybe a 10 V Zener in such a way that it Zeners when Vgs is > 10 V.

Like this: (Use courier or other fixed-width font)

1kV ---- | ---+ Drain || gate ---+---|| N-channel MOSFET | || ~ ----+ Source Zener / \\ | diode ----- | | | +--------+------- Vout

I also have to point out that you are operating a 1000 Volt transistor with, potentially, 1000 Volts across it. Normally, I would not recommend designing with zero margin.

--Mac

Reply to
Mac

well the upper fet is a source folower (non inverting), the botom fet is a comon source amplifier with negative gain, therefor overall negative feedback needs to go to the + of the op amp

your circuit has 2 subsequent inverting gain stages, wich is more of a problem for stability, and draws a fair bit more power from the 1kv

Colin =^.^=

Reply to
colin

the 8pf input capacitance sees the 100m in parallel with 1m so this isnt realy that bad, the 10k/100nf will determine the response mostly (1ms). you could decrease the 100nf untill you get the required response, you may need to put a resistor in series with it for stability/setling time.

if you still realy have problems geting it stable, reducing the gain of the output amplifier with its own feedback loop might help with stability, such as a resistor in series with a capacitor from the output to the botom fet gate.

I did a HV amp once before but had to use several mosfets in series to get the voltage, it was a nightmare, i never did fully work out all the diferent modes of oscilations that seemd to be present.

Colin =^.^=

Reply to
colin

Not to mention your FET model was no doubt useless below 10mA. An problem I've discussed at length on these pages. Remember, always test your spice models with bench measurements.

--
 Thanks,
    - Win
Reply to
Winfield Hill

Among many other things, I'm sure your FET model is useless below 100mA or so. An problem I've discussed at length on these pages. Remember, always test your spice models with bench measurements.

--
 Thanks,
    - Win
Reply to
Winfield Hill

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