Buck controller and minimum PWM on period ?

I'm making a 24 to 5V @ 12A DC-DC convert with accurate constant current limiting down to zero volts. After spending time designing a prototype using TI's UCC2541 synchronous buck controller, I discovered this IC has as a serious problem at low duty cycles. When the PWM on period is between 0 and 100ns the high-side FET fails to turn off correctly, causing catastrophic shoot through currents across low-side and high-side MOSFETs. I am now looking at different synchronous buck controller ICs.

It seems that all available ICs specify some minimum PWM on period (typically 50 to 150ns), thereby limiting the lowest controllable output voltage. I don't mind the control loop going a little chaotic at extreme low output voltage, but it must be capable of averaging out to a constant current into a short circuit.

Anyone know what is meant by controller minimum on period ? Does it mean:

1) Shortest on period regardless how low the programmed duty cycle. 2) Shortest on period while maintaining reliable control. Periods shorter than this are considered uncontrollable due to noise.

None of the buck controller datasheets clearly state what happens.

Adam

Reply to
Adam S
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It doesn't sound like the controller is having trouble at low duty, so much as your gate drive configuration and fet selection. Can you post your schematic?

This aside, the 2541 has a current limiting method that is specifically designed to hiccup into output voltages below a programmed level. In order to obtain the behavior that you are describing, you will have had to do something to the control circuit that you are not telling us.

The voltage control reference for this part is 1.5V. This is the inherent minimum output voltage that designers can assume for normal operation for this part. It is expected to fold back and start hiccupping below 750mV in the intended minimum output voltage configuration.

Using another controller to work outside this low voltage range is probably something the mfr would recommend.

RL

Reply to
legg

Correct, I am not using the built in current error amplifier. Instead, I have implemented average current mode control utilising the built in voltage error amplifier.

But putting this aside, the low duty cycle limitation is not a consequence of my control loop since I still witness this problem when I manually adjust the PWM duty cycle with a potentiometer i.e. without any control loop in the system.

I replaced the 0.003 Ohm FETs with much smaller 1 Ohm FETs so I could observe shoot through currents and waveforms more easily. Everything seems working fine, and I can even see TI's "Predictive Gate Drive" technology in action. But soon as ON period is falls below 100ns, something horrible happens, the high-side FET fails to turn off in time.

From what you say it seems the UCC2541 designers *never* intended this IC to be used for output voltages below 1.5V. My problem is that there are not many controller ICs around that will happily go down to 0V, and manufactures also often put too many features that limit the applications.

I'm looking at National's LM27241 with its 30ns minimum on time. This IC should then cycle skip at very low voltage/shorted output condition.

Adam

Reply to
Adam S

A simple method of avoiding shoot-through here, is not to use the synchronous rectifier. Replace the bottom fet with a schottky diode.

Synchronous rectification has it's place. Predictive gate drive of a synchronous rectifier has its place. Integrated comntrollers have their place.

What you probably need here is a simple buck regulator that will cycle-skip below a certain duty cycle.

OV or zero current are both difficult ("undefined") conditions to 'regulate', unless there's a means to reduce or reverse stored energy in the inductor during the free-wheeling period.

Synchronous rectification handles the zero-current condition nicely. A minimum or switched internal load will serve otherwise. For zero voltage, a nice freewheeling voltage loss comes in handy in the absence of a negative supply, but cannot be counted on to actually reverse energy flow in each cycle - so there's still a minimum current under which zero output volts can be regulated. The lower the voltage, the higher this current will be.

Cycle skipping will occur naturally in most (all?) single-quadrant regulators around the "undefined" operating conditions. This is naturally chaotic, but generally benign and is useful in stretching out performance extremes. However it likely unsuited to any 'predictive' technique. Perhaps that is what is actually being seen here.

RL

Reply to
legg

Thanks very much for your tips. Unfortunately, power dissipation restrictions don't allow me to do away with synchronous rectification. I am taking your suggestion of going a less integrated approach. Looks like I can use a simple voltage mode PWM controller IC along with a synchronous MOSFET driver IC. My calculations show that I need under 50ns of dead time, to avoid excessive synchronous rectifier diode conduction losses. I believe any of the adaptive dead time controlled MOSFET drivers can easily achieve this range, while still allowing ON times approaching zero.

Adam

Reply to
Adam S

You should sit down some time and ask yourself just what the circuit looks like, and how it is supposed to work, at 0V and 20A output. Where is the current flowing, and what are the voltages in and around the parts during the forward and freewheeling periods?

An ideal synchronous rectifier will maintain the 20A of current flow into the ideal short, through the ideal inductor, without the buck switch ever turning on.....

There are some notes on control of a normally-off syncronous rectifier at:

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RL

Reply to
legg

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