It's looking like I'll have to do something similar to that anyway. I have a PWM period of 100 and altering the duty cycle by 1 gives a change in output voltage of 2-3V. To get better than 1% regulation I'll need to dither the duty cycle.
I've got plenty of CPU horsepower available so I was thinking of a slowish loop to set the gross output voltage and a fast loop to just increment / decrement the duty cycle by 1 as needed depending on if the output is below / above the setpoint.
We've had a few days of sun here so it's more like a 15C rise :) That's still FAR too high though. The losses from the DC resistance are going to be around 50mW so I'd expect only a couple of degrees rise.
It is over-sized, it's a Vishay SUM33N20-60P-E3, 33A 200V. I wanted low on resistance. As it doesn't get very warm, and it'll be cooler still if I drive the gate harder, I'm looking at something like an IRF7820. There are 150V FETs but there's not much cost saving and 150V is a bit close for comfort.
I think I've settled on using a proper gate driver now. It takes the same board space as the collection of transistors and resistors I'm using now but will be much better.
Have a look a the schematic I posted elsewhere in this thread. I picked the multiplying SEPIC topology specifically so I would have a sensible ~50% duty cycle rather than a 90%+ one. It makes things a lot more controllable and it keeps the peak voltage down on the FET and diodes.
I swapped the Schottkys for ES1Js. It made no significant difference to the overall efficiency, >>> The output electrolytic (4u7 @ 400V) gets to around 40C as well. I
Hey, that's a coincidence! I put that exact part on order earlier this morning. LTSpice shows one of those by itself would give lower ripple than the 4u7 elctrolytic. Doesn't X7R give you roughly 50% the rated capacitance at the rated voltage though? I think I'll put two on the PCB to make sure.
Yes, I think the plan for the next revision is:
- Proper gate driver IC
- Swap the output electrolytics for ceramics
- Different inductors (tricky, all the alternatives are huge)
I like the look of John Larkin's design, using a dual inductor as a kind of autotransformer. I've ordered some parts for that as well as I want to see how well it performs in reality.
You're right, 350mA there gives around 400mW loss. Hopefully when I change that for a ceramic, a lot of that should go away. I haven't yet found the ESR for the 1uF 250V part I'm going to use but it should be less than 100mR.
Looks like you've only got a 4MHz clock on the uC then.
Or do a McGyver:
Run the timer CC register output into several port pins with series resistors connected to them in R2R fashion. Those resistors would all tie into a capacitor. A qualifier determines which ones will be set and this qualifier would become the "vernier adjust" in your loop. Run this through a comparator of your uC in order to square it up. Three port pins would already increase the granularity by a factor of eight.
Then you could also up the switcher frequency. Plus it can keep copycats at bay. They'd wonder "Now how on earth does this work?".
Sure looks like RF core losses then.
The 1750pF gate capacitance is also a bit high. Costs drive energy.
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But keep the gate capacitance low, meaning don't oversize the FET. There is always a sweet spot between Rdson losses and gate drive related losses. The latter would encompass losses in the gate driver itself but, more importantly, also linear-mode losses because the transitions become longer.
Yes, you are right. But it burns a lot of power in C1. I'd consider ceramics at least for that cap.
Every fraction of a percent counts :-)
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The higher density X7R can easily lose 50% capacitance. Manufacturers tend to not put that in the datasheets, maybe because it doesn't look good. But usually you can get that number from their support engineers. Main thing is, you really don't want the high ESR of an electrolytic, at least not for C1.
The DC resistance is ok, you just have to find a kind with less core losses. Since datasheets are typically lacking in that domain the only way to find out is often to contact the mfg's support engineers or try out a lot of inductors.
If that still isn't good enough maybe get a flyback transformer. They are ubiquitous and cheap these days.
That cap has a DF of .025 at 1kHz. That would be about .85 ohms at 1kHz.
TDK has some high-voltage, high-capacitance (for ceramic, anyway) parts. They have DF I like the look of John Larkin's design, using a dual inductor as a
On a ceramic cap the ESR is normally miniscule. Just stay away (in this case) from ceramic caps with deliberately increased ESRs as they would be necessary for those dreaded LDOs and stuff:
Two diodes in a SEPIC? The SEPIC schematic that I'm familiar with only has one.
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-- My liberal friends think I'm a conservative kook. My conservative friends think I'm a liberal kook. Why am I not happy that they have found common ground?
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The current version with its electrolytics is OK in that respect so somewhere around the 1% level is good.
The 4u7 electrolytics at 3R2 give a 2Vp-p ripple. A 500nF (if it drops that much) at 850mR gives a 1Vp-p ripple so it's certainly no worse and the losses should be much lower.
I posted the schematic earlier in the thread. It's a multiplying SEPIC so the big difference is the 2nd inductor is connected to the output of the first stage, rather than ground.
In this case, the first stage boosts 12V to 100V and the second stage adds another 100V on top of that. The peak voltage across the FET and diodes is only 100V but the capacitor in the 'middle' takes a beating.
Have a look at Linear's AN-1126. Figures 6 to 8 show the progression quite nicely.
It's a PIC24 at 8MHz so the timers run at 4MHz. I can increase to clock speed if I have to but only to 32MHz which would give 4 times the current resolution.
I think I see where you're going with this. This would be a 0-250ns delay to the start of the output pulse. The Rs and Cs would have to be chosen depending on the PWM frequency.
The FET would be driven from the comparator output. The OC pin(s) would go high, the cap would start to charge at a variable rate until the comparator switches and drives the FET on after a delay. When the OC pin(s) go low, I'd have to discharge the cap quickly via a diode so there's no delay turning off.
I can use the PPS functionality to map the OC output to multiple pins as well.
Sneaky. I like it!
It's also easy to bypass in software if it turns out to be *too* sneaky. Just remap the pin driving the FET back to the raw OC output instead of the comparator output.
The only thing to look out for is, for example, the transition between
27+(7/8) to 28+(0/8). I'd have to do this at the right time to avoid a single pulse of 27+(0/8) or 28+(7/8).
I've just stuck on a couple of big (40mm) toroids that I found in my junk box and the efficiency is now 86%. Unfortunately I have no idea what the core material is!
So, yes, at *least* 350mW is core losses in the inductors.
With the DC losses, I think >400mW split between the two inductors could explain the 15C rise.
Now the difficult bit. How to identify a 'low-loss' inductor.
Is a higher SRF better? It suggests a lower winding capacitance which may help.
I've found an FQD18N20, 830pF typical. It's 140mR though so it'll burn around 120mW.
The Miller feedback is certainly significant at the moment, the flat spot in the slope is around 70ns wide.
I've ordered a selection of inductors, I'll try that first. For the core material, most datasheets just say 'Ferrite' which is really helpful!
This simple little switcher is turning out to be quite interesting.
how do you get that CC value converter to 3 more bits?
Please disregard this post, Dave explained it nicely, didn't know the meaning of vernier, now do :-)
Very nice trick. Microcontroller comparators are often quite slow and has large VOS, but since this is in a closed loop, the slowness will only set minimum duty cycle as the delay is just an offset of the loop duty cycle.
That could possibly even be auto-calibrated by the uC. It could monitor the output voltage and find out "Whoops, it's not supposed to jump here" and then truncate the 7/8th step.
But now you know that a lion's share of the losses is indeed core losses. In the end you'll probably have to try a lot, assuming you must live with catalog inductors. Or contact a good vendor. Wuerth would be one of them on your side of the pond.
Yes, it sure does.
Unfortunately not. Absent any datasheet info it's as difficult as picking a horse at the races. Best bet is to approach manufacturers and tell them you want to operate a SEPIC around 40kHz, and which of their inductors would be the least in core losses. The reason is that they won't tell you where they buy their core materials.
And that's where the FET goes linear. If you have to push efficiency to the max you'll have to find the sweet spot in the compromise between Rdson and capacitances. In your case Cgd is very important. I usually get a lot of models and try it on SPICE. It's always a bit of a pain when such a job needs to be done in summer because then the PC drives the office temperature way up. For Saturday the forecast says 43C ...
Yup. That's like saying "contains barley" :-)
Those are great learning experiences because now you get face-to-face with every loss contributor in the switcher. The next design will then become so much easier.
That does work but I need to make the output capacitor on the first converter quite large to keep the 50V stable. I also end up with two loops to control and the 2nd converter has a very low duty cycle, which I'm trying to avoid. If the load current was reasonably constant I could possibly run one at a fixed duty cycle.
It splits the ratio down to 2x 1:4 rather than a single 1:16 which is nice but it makes things a bit more complex in the software driving it.
If the load current suddenly drops to zero, or there's a short, I don't want it to go *phut*. At the moment, If the output voltage rises to, say, 10V above the setpoint, I've lost control because the load current has suddenly dropped. This takes a few milliseconds to happen which is plenty of time for the software to notice and cut off the FET drive until it's back within range. It'll do a sort of burst mode control with very low loads.
I don't like the idea of burst mode control with two interacting converters.
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