The device offers the following sampling rates on the delta-sigma ADC:8 16 32 64 128 250 475 860
The 16/sec conversion rate would alone reject 60Hz fairly accurately, but there is no similar option for 50Hz.
Sampling at the highest speed (860/sec) and accumulating 14 or 17 readings respectively (and then dividing the total by the number of samples), would do it, but then we don't get the natural noise rejection of the slow ADC reading rates.
It seems that the best compromise is: For 60Hz rejection, use the 16/sec reading rate directly. The averaging feature is still available but is not necessary for 60Hz rejection. For 50Hz rejection, use the 250/sec reading rate and average last 5 readings.
However, I can't get my head around whether the 50Hz option will really work.
It would obviously work if one added up 5 readings and divided it by 5
- a process which would take 20ms and that would be exact. Then you start with a freshly initialised accumulator for the next 5. So the system would deliver one reading every 20ms, only.
But will running (what I think is called) a FIR filter, with the last5 readings held in a FIFO queue, have the same 50Hz rejection effect? That delivers readings every 4ms.
I think it will work because the queue will contain 20ms' worth of readings.
Many thanks for any insight. It's quite a subtle question!