asymmetric stripline

"John Larkin" a écrit dans le message de news: snipped-for-privacy@4ax.com...

Simulation pix map 400 pixels high by 1600 pixels wide.

INPUT PARAMETERS:

Layer Thick Er Specifications Copper Plane Top 1.30 3.20 Open w=0.0 off=0.0 Laminate Layer 1 12.00 4.20 64.3% 3.2/6.0 Signal Layer 1 1.35 4.20 W=13.0 Etchback=0.00 Laminate Layer 2 24.00 4.20 64.3% 3.2/6.0 Copper Plane Bottom 1.30 3.20 Open w=0.0 off=0.0

Rdc_trace_1= 38.67 milliohms/in 20C DC resistance by pixel count: Rdc_trace_1= 37.291 milliohm/in. C = 3.462 pF/in L = 8.709 nH/in. Er = 4.200 Delay = 173.626 ps/in. Zo = 50.158 Ohms

Friendly, Robert Lacoste

Good link!. Looks like fun. Thanks.

Thanks. I'd used Er of 4.5 for the dielectric, so my 12 mils guess is pretty close, maybe even a bit below 50 ohms. This is for a test trace that I'm piggy-backing onto a production board; I'll TDR it and post the results. It will include various traces and vias, and do some "reference plane" switching.

That program looks like a fancier version of ATLC. It still appears to need an external bitmap generator. But there seems to be no HELP.

John

My recommendation: contact your board house. They (should!!) have good calculation capabilities for the specific board material and stackup you are dealing with, and can even tell you tolerances. I've had very good service on this sort of thing from the couple of board houses we use.

I do have a nice spreadsheet that will come close on things like this, and on differential traces and various other things, but when push comes to shove, the board house is my backup.

Cheers, Tom

Check more than one board house, they are always a little different.