Really? ;)
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
It's amazing how many people seem to think that is what volatile does. You want to transfer data between threads (or interrupts and main loop code)? Use volatile - it is the same as synchronisation. You want to be sure that your transfer of 32-bit values on an 8-bit system are atomic? Use volatile - it implies atomicity. You want to make sure a calculation is done outside of a critical section? Use volatile - it forces an ordering on your calculations. You want to make sure that the DMA sees the same data as your cpu despite the cache? Use volatile - it forces cache coherency. You want to make the compiler forget what it knows about your "bool" variable? Use volatile - it tells the compiler that you are breaking the rules.
And so on.
Assuming that "volatile" has superpowers is almost as common as forgetting to use it when it is needed, and then claiming the compiler's optimiser is broken.
Even knowing the instruction sequence in processor code memory does not guarantee the order of bus sequences in modern processors.
You need memory barrier instructions to guarantee the sequence, but you'll mess with the processing performance then.
-- -TV
It was on a 68020, so I nearly had that problem. I did have to manually figure out which instructions and memory reads seen on the bus actually had an effect.
Later processors would have been worse, of course.
You also need the right kind of memory barrier - there are many levels of ordering for a modern processor. You have the compiler level (volatile is enough to force an ordering there with respect to other volatile accesses - but not with respect to non-volatile accesses). Then you might have write buffers in the cpu core, then caches with write-back, possibly cross-switches with buffering, then memory controllers with buffering and re-ordering.
Fortunately, it is very rare that you actually /need/ a particular sequence of accesses on the final memory bus. Usually you only need it on internal peripherals on a SoC, and that is easier if you have your MMU set up correctly to skip caches and buffers.
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