another goofy boost converter architecture

It's just a handy thing to click on to see the drain current waveform. It's harder to hit the pins of a part.

This thing runs really slow, like 5PPM of real time, but I suspect it's the comparator models.

Yes, good point. I find myself doing that sometimes too for the same reason.

boB

Jim-out-of-touch-with-reality-Thompson has been that way for years. It seems to be more his culture than his ageing brain cells.

He's spent his career designing integrated circuits, not board level products that can contain inductors and transformers, and he's not exactly got a lifetime of expertise in the area.

You do design inductors and transformers into some of your parts, but you don't seem to go to the trouble of designing the wound parts yourself - if you can't buy it off the shelf, you don't bother.

And you don't seem to be picky about measuring the properties of the parts that you do design in.

In today's "Trouble" converter, L1 and L2 each have an inductance of 5uH, and a series resistance of 60 milliohms, but no parallel or inter-winding capacitance.

Would it have been that difficult to measure the self-resonant frequency? Many manufactures list it in the data sheet for their parts.

I've yet to see you exploit LTSpice's John Chan hysteretic core model for real inductors. One can't - yet - use it for coupled inductors, but the one time we compared it with reality, it did pretty well.

You may not be confused about magnetics, but that's probably because you don't pay any attention to the confusing details.

Insanely superficial design ...

There are two camps here. Some of us simulate only to better understand the circuits. The actual schematic, for production, may not resemble the Spice model too much.

Some other people feel the need to have their Spice model be the exact circuit that they will build. They sometimes get pickey about the conceptual modeling idea. These people also get upset if I post a sketch of a circuit without parts values.

So name the node - that makes life easier still.

Spice models have a feature in common with real circuits - they react to th e real values you've put in, rather than the values you intended to put in, and thus help you to "proof-read" your circuit diagrams.

It's rather handy if you can simulate exactly what you are going to ask pro duction to document and build - it doesn't catch every error, but it catche s enough to be worth the extra effort.

That's not being picky about the "conceptual model" approach - a circuit di agram without parts values is less informative than one that includes them

- putting in parts values increases the number of people who can make sense of the circuit diagram, and this informs more of your readers.

It may not increase the number who take you seriously, and who might risk b uying something you designed, but that does depend on the part values and t he circuits.

My dozens of _commercially_successful_ switcher designs disprove your mouthing, lying, whining and ranting.

I do have you in a tizzy >:-}

And more fortunate, many others on this group are now discovering that you're primarily full of it, and are calling you on it.

Enjoy ;-) ...Jim Thompson

Lacking proof, we'll take you word for having designed parts of switchers long ago.

You were obviously mentored by Always Wrong. You have adapted his technique of making a fool out of yourself and then declaring victory.

Call me on it by posting a better efficiency equation to replace the one that you don't like. You know, do some engineering. Say something on topic.

Oh, my HC14 switcher comes out needing one less part than using an LT3757. And, if the fet gate drive requirements are modest (which I suspect they will be) I'll have a schmitt section or two to use elsewhere, even better. The thing I'm designing drives a pulsed laser at 25 volts and 120 amps (3 kilowatts electrical, 1.5 KW optical out), powered by 9 volts, and I have 1.5 square inches of PCB to do it in.

Well, sort of this...

Use the following for your behavioral source for efficiency:

V= 100 *idt( I(R6) * V(VP) / ( I(R8) * 9 ))/time

It does not go over 100%. If you see a flaw in the math, please ping me.

Cheers, JohnS

Look up GenRad PSP testers. Off-line switchers designed before there were any off-the-shelf controller chips. These were the ones I've mentioned on this newsgroup before, ran so cool, I removed the flag heat-sinks, then mistakenly grabbing a flag to see how cool they were... they _were_ "cool" but "hot", much to the joy of my technicians ;-)

Well? You _are_ in a tizzy, ignorant as a stump and caught at it.

I think you've been sniffing turd dust.

You couldn't engineer your way out of a paper bag.

There are several fundamental flaws in the way you tried to evaluate efficiency. Any student-level lurkers want to set Larkin straight... I have him set up on the tee, all you have to do is swing the club ;-)

Your "skeptic" is 54.55% "efficient".

Draws 10A when starting up... draws only ~110mW at equilibrium.

Exceeds the absolute VDSmax spec (30V) of the Si7218DN by 2V.

And you're so stupid you don't realize what's wrong with your "efficiency" equation.

You can't cure stupid, stupid is forever. Larkin is "forever" >:-} ...Jim Thompson

Larkin rants about stuff for which he has no clue.

Most off-the-shelf I/C's have lousy models because the manufacturers are trying to conceal IP, circulating only behavioral models.

Unfortunately they hire math PhD's with no hands-on engineering experience to create these models.

On the other hand, foundries like XFab, TSMC, UMC, ON (nee AMIS), Atmel, He Jian, etc. (I could go on and on and on... I have libraries for 95 different process houses), have very accurate device-level models. If they were not accurate, chip designers like me would take their business elsewhere.

In my end of the business failure of chip to match simulation only occurs when there's a manufacturing fault. ...Jim Thompson

I spend most of my spice time trying to get the model to reflect real results. Very pokey.

RL

You sure can't do it yourself. Sad old has-been; I'd feel sorry for you if you weren't such a creep.

It does not. The 9v supply current ramps up from zero and peaks at about 900 mA, by design. It does use very little power after the cap is charged, again by design.

That's not the fet I would use. I grabbed it out of the LT Spice parts library, just for the sim. I'd use a 50 or 60 volt fet in the real thing. Something with less capacitance, too.

You can't articulate what that problem is. You're hoping that some "student-level lurker" will come along and help you out.

I certainly can.

I used your very .ASC file. So, if those are ideal inductors, so are 'mine". Only thing I changed was I did a long integral to average input power. Your scheme, while flawed all around, was also way too short.

Baloney. I ran your very file... in LTspice. I didn't try it at all in PSpice.

I'll give you a pass on that >:-}

Come on, John, you cretin. If you think you're right, tell us how your equation works. (It does things you don't even understand. Give us your glorious explanation first :-)

Your design is a crock-a-shit, as Vladimir more politely put it, " ...Jim Thompson

I advise everyone to run Larkin's crock .ASC file for themselves.

Hit the wrong key :-(...

Your design is a crock-a-shit, as Vladimir more politely put it...

"May I suggest septic converter? Looks like even better name for the circuit."

"Another flawed design. Again, C1 does hard discharge in L1 L2 M1. Why can't you just make classic transformer flyback?"

"I am hostile to flawed designs. Especially if advertized as new and great."

"Aren't somebody like you supposed to grew up from diapers design league?" (I like that ;-)

"I do not like conceptually wrong designs." ...Jim Thompson

At time T in the sim, that gives the average of efficiency since startup. That's not what I want to see; I want to see the "realtime" efficiency vs time curve. If course, some amount of time averaging is required to get a usable plot, which is why I have filtering.

Your equation has a gotcha too. 1 mw/1mw makes the same contribution to the efficiency integral as 1w/1w, which doesn't seem fair to me. The actual averaged efficiency might better be (integrated energy out) / (integrated energy in). That would be the ratio of two integrals, not the integral of one ratio. But again, that's not what I want to see.

There is no unambiguous, clearly right definition of efficiency here. My equation is what I want to see.

Here 'tis...

And the efficiency IS 54.55% ...Jim Thompson

Your equation "clips" products greater than 120 or more negative than zero. What kind of gimmick is that?

The integral needs to encompass at least one cycle. Your "integration" is way short.

Unfortunately LTspice doesn't implement one of PSpice's Probe niceties, AVGX... average over t=X. ...Jim Thompson

OMG, you're right! It peaks at 10 amps! For 20 femtoseconds!

I intend to have bypass caps across the 9V input from the customer. You may as well complain that the current to charge them will be infinite. I bet I can get a million amps in simulation, easy.

Vlad was not merely rude, he was wrong on both his criticisms. The fet drain current isn't "infinite" and the drain voltage overshoot isn't "infinite." Neither is a practical problem. I assume you agree with him about the infinities.

But so far, you have said nothing substantive. I don't think you can.

I'm going to build this, it will work, and I hope to sell about 10,000 of them.

Baloney, it does that for multi cycles, expanded view...

That'll learn ya... post an LTspice schematic and you're subject to verification... the baloney stops here ;-)