another goofy boost converter architecture

Surprise! Fets in a switching regulator have high peak currents! The customer won't see that, because I'll have bypass caps on my board.

The 9 volts will actually be present for a while before the boost inverter is enabled. It's only turned on when they want to use the laser. This will work.

Huh? The plotted current is IDRAIN!

The VCC current of the two LT1011 devices is a single spike at t=0, and nada thereafter. You're grasping at straws. Vladimir's assessment is correct.

Only when it suits your purposes ?:-)

I ran it clear out to where equilibrium was reached. Averaged the 9V current over 500us out there at the end.... 110mW input... load is

If you really need support only a very light load, there's much better ways to do it.

Do feel free to post all your "cute" circuits as LTspice files... makes for great fun >:-} ...Jim Thompson

You're flailing. I like to see you flail :-) You didn't even look at the waveforms I posted. You're just scrambling to cover your own ass. ...Jim Thompson

That's after the cap is charged up. We're idling, waiting for the next laser pulse. There's very little battery drain in this state. What matters is the 3 kilowatts of pulsed laser power, and the net load on the battery in operation. The efficiency that matters is when we're recharging the caps after a laser pulse, and it will be high.

When the laser is not in use, the customer will tell me to shut down, go to low power mode.

I threw the R5-R11 values in there for loop simulation, and because I

You can't understand my application, but that's not the point. This is a new, at least to me, switcher topology, and it will work fine, and you and Vlad just don't like it.

There is, in theory, no load once the caps are charged up, until the next shot. I will scale up R5-R11 in the real thing, to a few megs maybe, as that's the only thing discharging the caps between shots... well, that and D1 leakage. What matters is the efficiency during recharge after a shot, with the caps ramping from roughly 38 volts back to idle at 48. At 1 milliwatt into R11, I don't much care if the efficiency is 50%.

Excuses, excuses, flail, flail, flail...

I love it >:-} ...Jim Thompson

Not excuses, engineering/

Engineering? I think not. What you love is trying to be vain and mean. You're not very good at any of the above.

The surge current that you complain about is the same thing Vlad complained about: the 2 uF cap, C1, has to be charged. That's trivial, given that I'm going to expect the customer to charge maybe 25 or 50 uF of input bypass capacitor.

It's not a problem.

Drain flyback voltage isn't a problem either.

What are the specifications, load, etc.? Let me know and I'll whip up a simpler way. ...Jim Thompson

Okay.

ISTM that a better metric to determine how happy I would be with it, if it were mine, would be watt-seconds in the output capacitor divided by watt-seconds supplied by the source, calculated over the charging interval.

For curosity, I did that and I see that it puts 4.6 w*s into the output capacitor while using 5 w*s from the source. That would be about 92% efficient. Not bad.

Anyway, not my project, so have fun.

Duh!

An efficient way to do it...

I'll convert this to modern technology in LTspice and post it. ...Jim Thompson

Simply not true. I often use LTspice to play with a circuit to see what it might do. I also despise topologies (circuits without any values or described purpose) which you post a lot. Then again i do not design ICs which pretty well better work mighty close to right the first time. The IP $ in a mask set is not trivial.

?-)

Not true? Not a single person in the world works that way?

I often use LTspice to play with a circuit to see what

You must despise wikipedia and the majority of EE texts and reference books, too.

Then again i do not design ICs

Right. The problem with pc board-level design is that it's not feasible to simulate many non-trivial designs. But then, we can ECO boards.

Converted to modern elements, in PSpice...

Vout levels off at about 6 milliseconds, but none of the waveforms change. What's the drain waveform look like? What's the current in DZ1 look like?

It's displaying the integrated energy ratio, but I want to see realtime efficiency.

I can't use a boost converter in my application. The inrush surge into 4 millifarads would take the system down.

It's Pspice, not LT Spice, so most of us can't run it even if you posted the netlist.

Oh, I see: the graph time scales don't align.

...Jim Thompson

I'd take a close look at the oscillator. It doesn't seem possible it could run due to the pullup resistor R1 going to +5. You would think the logic would lock up as soon as HB1 output switched to a low logic level.

Also, the 5V swing on C1 looks like it would drive the input of HB1 above

Driving 5 HC14's in parallel into a 2N2369 to ground looks like it would cause some hurt somewhere.

LTspice is supposed to be able to run PSpice netlists. There is no schematic so I don't know how you select which waveforms to view. JK

The inductor current ramps up until the drop across R2 hits 0.2, and then the rest of the stuff pulls the HB1 input low, so it does oscillate. But it is messy. The low side of C2 could have been grounded, but I'd just as soon do it the way I did it.

Yup, it will bang the ESD diodes.

Driving the mosfet gate is fine. But the the c-b junction of the 2369 gets involved. Even messier.

There is no netlist.

Something like this might work for a really cheap booster:

Yep, Expanded views. ...Jim Thompson

That connection provides hysteresis. Actually didn't need the 'HC14's, could have used 'HC04's instead. I've used that scheme a lot on custom chips to provide a symmetrical digital delay... mostly to avoid crowbar problems with H-bridges.

I've addressed that in multiple posts involving using inverter packages as oscillators... all it does is affect the time constant.

There is a PSpice schematic

I can provide that. Actually you would need both the .CIR file and the .NET, concatenate as .CIR, works just fine

PSpice Schematics is a much more user friendly GUI so, when clients request running under LTspice, I just run the .CIR. (In LTspice, File, Open...)

Still need to address the initial surge which you said would bring down the system. Maybe a switched-in soft-start resistor? ...Jim Thompson

I don't see a way to do "spot" efficiency... you'd need to do a delta between two values separated by some appropriate time value.

The continuous computation _is_ pretty much linear.

This should work in LTspice. You'll need to edit with the appropriate library paths, and use your own common device models...

• C:\Projects\Expments\SED\Switchers\Switcher_SED.sch
• Schematics Version 15.7.0
• Tue Jul 09 10:42:37 2013

• Schematics Hierarchical Netlist * Q_Q1 N_2 N_1 0 Q2N2369 C_C2 N_2 N_3 220pF R_R6 N_1 N_4 5.1K V_V3 N_5 0 +0.2V V_V2 N_6 0 +5V X_HB1 N_2 N_7 0 N_6 74HC14 X_U1 N_8 N_5 N_4 N_6 0 0 TLV3501 R_R1 N_6 N_2 10K D_D8 N_9 N_10 D1N4148 V_V1 N_11 0 +9V R_R2 N_12 0 0.2 X_MN1 N_14 N_13 N_12 sQ3426EEV D_D3 N_14 N_9 DI_B1100 R_R7 N_3 N_13 10 R_R8 N_8 N_12 1K R_R3 N_11 N_15 0.1 L_L1 N_14 N_15 10uH IC=0 X_DZ1 N_8 N_10 MyZENER PARAMS: BV=47V IBV=1m RS=1 IS=10f
• CJO=10pF X_HB2A N_7 N_3 0 N_6 74HC14 X_HB2B N_7 N_3 0 N_6 74HC14 X_HB2C N_7 N_3 0 N_6 74HC14 X_HB2D N_7 N_3 0 N_6 74HC14 X_HB2E N_7 N_3 0 N_6 74HC14 C_C1 N_9 0 10uF .LIB "C:\PSpice\SpiceModels\TI\TLV3501.lib" .LIB "C:\PSpice\SpiceModels\Vishay\SQ3426EEV_PS.lib" .LIB "C:\PSpice\DeviceLib\Zetex\Diodes_Inc_Zetex.lib" .END ...Jim Thompson