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een looking at the numbers with JLC and they are better than some, but You aren't going to route 0.4 mm BGAs with their capabilities. I'd have to look at the specs in detail for a given footprint, but I don't think they can e ven do 0.5 mm BGAs. Pretty much anyone can do 1 mm and most can do 0.8 mm p itch BGAs, but I don't think they are considered fine pitch. Exactly what d imensions are you talking about JLC being able to do?

at. I was told for my 12 year old design with 10 mil drills they would like ly bump that up to a larger size. The language on their page talks about up sizing annular rings to 0.15 mm (6 mil). That gives via sizes of about 0.6 mm or 24 mil. How are you going to route a 0.5 mm BGA with 0.6 mm via pads ? Does that work? For the 0.5 mm CPG196 Xilinx wants via pads of 0.27 mm (1

1 mil) and via holes of 0.15 mm (6 mil). I don't see that happening on a JL C board with 0.2 drill and 0.4 mm pad minimums. Looks like they can't even do 0.8 mm pitch with 0.25 mm drill and 0.51 mm via pad size.

r XC6SLX16-2FTG256C in a 1 mm spaced BGA package. Still not easy to route o n a tight board with all the vias, but possible without using a more expens ive board process. I don't think the rest of my board could be built by JLC as they would not have the parts in stock... not all of them anyway.

ey don't show any vias for breaking out the connections, do they? That's th e part of using BGAs that requires finer PCB processes. No point in working with 0.4 mm pitch BGAs if I can only access the first row or two of I/Os.

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n inner rows of a BGA requires vias to route on another layer. Once on othe r layers you don't have pads in the way, so routing is freer. On the compon ent layer you have pads and vias so the only routing is from pad to via whi ch is typically a very short route of no consequence and routes from the ou ter row which is a gimme and the next to outer row which can be routed dire ctly given the trace space limitations you are addressing. If those dimensi ons are too limiting to route the next to outer row on the same layer, vias can be used.

other layers. This must be addressed on any BGA of more than 16 pins. I se em to recall some BGAs that have a break between the outermost rows and the inner rows to facilitate routing without vias between the pads. I think th ese are still hard to route as the open space needs to support an awful lot of vias.

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I don't know why you are talking about the number of layers. The problem i s getting vias in between the pads. If you follow the article you will fin d he calculates a drill size of less than 8 mil and chooses a 6 mil drill s ize. So JLC would not build this design, at least not to the user's spec.

Was this what you wanted me to see?

As to the issue of the number of layers required to route the BGA "escape r oom", they don't actually show routed boards, just a tiny section with the BGA. I would also point out this is only a 64 pin BGA. The parts I would be interested in using are typically a much higher pin count and/or finer g eometries. Then there is the issue of routing the signals after escaping t he BGA room. On the board I might respin with a new FPGA the width is only 21.6 mm. and a FT256 part is 17 mm. So very little room outside the BGA t o route on two sides. The majority of the signals are routed in one direct ion and an inner layer is essentially devoted to routing these "long lines" .

I've been discussing this in a few different forums and it has been an educ ation. I found that LCSC sells Xilinx parts for around 20% of what they ar e listed at Digikey. If they are real Xilinx parts that's pretty amazing. They also sell a number of the parts I use on my currently produced board, but not at so great prices. Then there is the issue that if I wanted JLC to build them, they don't work with all the parts that LCSC sells. Without assembly JLC is not so useful to me. I don't believe they assemble user s upplied parts.