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AD8045 mystery

Hi, all.

So I have this SiPM/MPPC front end. It has pop options to use either an On Semi MicroFC-10010 1-mm SiPM chip or a packaged Hamamatsu S13362-3050DG 3-mm MPPC with integral TE cooler, both bootstrapped by a SAV-551+ running at 20 mA. So far, it all works.

(The SAV-551+ is amazingly stable--I've got a shipping product that runs a very similar bootstrap across a 2-inch FFC cable. Bandwidth suffers a bit, but it shows no tendency to oscillate.)

The mystery is in the TIA stage. It's a vanilla op amp TIA made from either an ADA4899 (600 MHz, 300 V/us) or AD8045 (1 GHz, 1300 V/us @ Av=1), which are pin compatible in the 3-mm LFCSP package. Both are voltage feedback amps.

I'm seeing a 3 dB bandwidth of 220 MHz, together with a faster rolloff than I expect: -3 dB @ 220 MHz, -9 dB @ 320 MHz. It's not slew limiting, because the waveform looks pretty good on a 3-GHz scope (TDS

694C) and the rolloff stays the same when I drop the input by 6 dB.

The layout is pretty tight (the whole board is only an inch square), so getting enough stray capacitance across R_F to account for it is implausible--it would need about 1.4 pF. DecouplingBypassing is good--

For test, I removed the 0-ohm jumper that connects the bootstrapped SiPM to the summing junction, and added a 1k input resistor, forming an inverting amp with a nominal gain of -0.5.

That's connected to the terminated end of an RG-174/U cable going to a PTS-500 synthesizer. The output goes via a 10-ohm resistor into a properly-terminated 50-ohm cable (the TDS 694C is 50-ohm only).

Here I'm expecting a bandwidth somewhere between the datasheet's 1 GHz @ Av=1 and 400 MHz @ Av=-1, but it's way off. There's no visible change when I put the jumper back in, on account of the swoopy bootstrap.

So where do you suppose the missing factor of ~3 in bandwidth went?

Thanks

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com
Reply to
Phil Hobbs
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Do you have enough bootstrap gain?

Reply to
John Larkin

330 ohm bead and 1 uF 0603 to ground from both supply pins. Supplies are +5/-4.

Yes, the BW hardly changes when I disconnect/reconnect the whole PD/bootstrap thing by way of the 0402 jumper. I also verified that the step response gives about the same answer. Using a very nice 30-ps Leo Bodnar pulser, the amp's rise time is about 1.5 ns, underdamped with ~20% overshoot. (Initially I had 0.3 pF across the 511-ohm R_F, but ripped it out to verify that it hadn't been mis-stuffed.)

This board has solder flux about 2 inches deep at this point. ;)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com
Reply to
Phil Hobbs

Sorry, no help here. But curious what you mean by "bootstrap"ing a MPPC diode?

Thanks!

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de 

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt 
--------- Tel. 06151 1623569 ------- Fax. 06151 1623305 ---------
Reply to
Uwe Bonnes

Same as an ordinary PIN. You get rid of the effect of its capacitance by using a follower to force the anode to follow the cathode at AC.

That way the high frequency noise floor is set by

omega Cdiode e_Nbootstrap

and not

omega Cdiode e_Nopamp

Those numbers are more than 20 dB different, so a bootstrap is a win.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com
Reply to
Phil Hobbs

That is equivalent to connecting a negative capacitor across the photodiode. Of course, the cap value is exactly correct.

Reply to
John Larkin

Yes, because the photodiode capacitance is what governs the value of the negative C, and the follower's voltage gain is always less than unity.

My best one has a gain of 0.9997 at DC, and better than 0.995 out to a few megahertz, as measured by the bootstrap bandwidth increase. (It's hard to measure it any other way.)

You don't usually need it that good for noise purposes. If the op amp's voltage noise is N times the bootstrap's, the two e_N C noise contributions become equal when the bootstrap gain is

A_V = 1-1/N,

and another factor of 2 knocks the op amp down to a 1-dB perturbation. Thus a gain of 0.95 is usually enough for noise purposes unless the op amp is horribly noisy.

In our QL01 quantum-limited nanowatt photoreceiver, we use an LM6171 for the TIA stage despite its fairly gross e_N of 12 nV in 1 Hz (typical). The noise of the 10M feedback resistor is 400 nV in 1 Hz, so you might think we were fairly safe with no bootstrap, but no.

The e_N C noise starts growing linearly (in volts) at the RC corner frequency of the feedback resistor times the total input capacitance (diode plus circuit), which might be

f_N = 1 / ( 2 pi (20 pF) (10 Mohm)) = 800 Hz,

so with a 1-MHz bandwidth the output noise would be around 15 uV in 1 Hz, except that the LM6171 would run out of gain and bandwidth before it got there.

With a BF862 or equivalent bootstrap device (e_N ~ 0.9 nV in 1 Hz), we'd only need a gain of 0.96 or so for the TIA noise to be a 1-dB level perturbation. So why worry about getting so close to 1.0?

The reason is a hidden gotcha: In a bootstrap there's a pole/zero pair near f_N that doesn't quite cancel. This leads to to whoopdedoos of order (1-A_V) in the impulse response at late times, a matter of a few percent with A_V = 0.96.

A bootstrap gain of 0.995 makes for dramatically better measurements.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com
Reply to
Phil Hobbs

I was going to suggest looking at the 'speed' of the light source. But the above seems to point to something 'in' the amp stage... (Is that right?) (And maybe check the light source rise time anyway?)

George H.

Reply to
George Herold

This has the SiPM and bootstrap disconnected (0 ohm jumper removed) and a 1/20W leaded 1k resistor bodged in to make an inverting amp with a gain of -0.5.

I'm looking at the trace capacitance to figure out if that might be it. There's about 3/4 inch of 10-mil trace on the summing junction, but that ought to produce a high frequency peak if anything. hard to find

1.4 pF across the feedback resistor. Once I'm back in the lab I'll measure a bare board with a Boonton and see.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com
Reply to
Phil Hobbs

What's the board stackup? Not the specified one, but the real one. I've been burned by what some of the fast-turn proto houses do.

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--

John Larkin         Highland Technology, Inc 

Science teaches us to doubt. 

  Claude Bernard
Reply to
jlarkin

Are you using vias through internal planes? Each via may add 0.5 pF stray capacitance or even more.

--
Fletto i muscoli e sono nel vuoto.
Reply to
dalai lamah

The Saturn PCB design software does via calculations. A big one can be many pF.

--

John Larkin         Highland Technology, Inc 

Science teaches us to doubt. 

  Claude Bernard
Reply to
jlarkin

Can you tap that PTS-500 synthesizer input right at its loading on your board and verify its not rolling off for some reason?

Reply to
Fred Bloggs

The SJ capacitance is 2.4 pF, as measured on a Boonton, which is about twice what I expected. That seems to be the issue--in simulation it produces a pretty big gain peak, which reduces the bandwidth.

Time to Dremel the ground plane. :(

Cheers

Phil Hobs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com
Reply to
Phil Hobbs

Hah, my first TIA I took a belt sander to the ground plane. (Terrible layout on my part I had the input trace snaking around.)

Finding the trouble is good. George H.

Reply to
George Herold

How many layers?

Maybe section the board to see what the stackup actually is.

Here is a Dremel-optimized SMA connector.

formatting link

formatting link 

--

John Larkin         Highland Technology, Inc 

Science teaches us to doubt. 

  Claude Bernard
Reply to
jlarkin

Only four, but of course ground is L2 and there's an L3 ground pour in that area. It is PCBway, so maybe they did the same thing to me. (A generally very good outfit in many ways, especially price and delivery.)

Monday I'll look at it under the good microscope. (About three years ago, I got a beautiful Mitutoyo FS-110 with 2x-50x long working-distance objectives for $2k on eBay. Apparently the guy didn't know what he had, because he shipped this massive precision instrument in a cardboard box with foam peanuts. The box was a mess when it got here, but the scope survived because it's a beast.)

Nice.

We've had that problem too--you need some extra pad area for the solder fillet, but that makes a nasty capacitive discontinuity at the connector.

Cheers

Phil Hobbs;

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com
Reply to
Phil Hobbs

Several of the chinese quick-turn houses make 4-layer boards with very thin (like 4 mil) outer dielectrics. Maybe they roll process the outers and glue them to a core or something.

I sheared and sandpapered the example I posted, and shot it with my super-good microscope

formatting link

The impedance of that SMA edge-launch connector, center pin to the four ground pins, is about 100 ohms in free air. So the PCB has to be about 100 in the pin region too. We've worked that out, cutting away inners and paving over the bottom with ground. We simulated the whole geometry with ATLC to get the dims right. That was cool.

The case I posted was testing a laminate sample, 20 mils thick.

The $1.50 edge-launches are just as good as the $12 microwave connectors if the layout is right, at least as far as we can resolve with 30 ps TDR.

I sometimes cut away layer 2 (or more) under critical circuit nodes. My triggered Colpitts oscillator has a driven guard patch on layer 5.

You bootstrap photodiodes, so you might bootstrap the PCB too.

--

John Larkin      Highland Technology, Inc 

The best designs are necessarily accidental.
Reply to
jlarkin

niptechnology.com:

I believe the common process for 4 layers is first a core with the inner layers and then sandwiched with pre-peg and copper to make the outer layers

thin outer dielectrics means traces to things like DDR ram does have to be mile wide

Reply to
Lasse Langwadt Christensen

Thin, actually?

A 50 ohm microstrip on 4 mils thick FR4 dielectric is 6 mils wide. A

75 ohm trace would be 2 mils wide. 
--

John Larkin      Highland Technology, Inc 

The best designs are necessarily accidental.
Reply to
jlarkin

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