Analog Device's AD1871 24 bit analog to digital converter

Not that particular part, but in general for most recent-generation serial-data-bus AD parts you really really have to make sure that you're obeying the clock rise, fall, hold, and skew times.

A quick look at the AD1871 datasheet makes me see that they don't specify rise/fall times. That makes it hard to obey them to the letter! Wjhen daisy chaining things must get exponentially worse.

In my limited experience with their serial-control-bus DDS's, a typical PIC or microcontroller resulted in flaky operation because the rise/fall times of the serial bus clock being in the 3-4ns region was way too long.

Tim.

Thanks for the reply Tim. I finally found the problem. The data sheet has yet another mistake in it! The data sheet is worthless. Bit_Clk high to low, not low to high clocks in the LRClk.

Dale

The analog design guys tend to do truly bizarre digital interfaces, then explain them badly and often just plain wrong. Timing diagrams can be especially bad. They also don't like to distinguish between edges and levels. "When LE goes high, data is transferred..." could mean either, and usually does.

John