AI Will Create More Jobs Than It Eliminates By 2027

What's that supposed to mean?

Polar orbits that never fall into the shadow of the earth?

So you're summing the FPGA outputs via resistors? How many bits do you anticipate using? You still have the subharmonic spur problem unless you're using the full width of the phase accumulator (or at least all the bits that change).

Cheers

Phil Hobbs

Our XO is 25 MHz. We use a PLL inside the FPGA to multiply that to 250 MHz, which clocks the DDS phase accumulator and some other logic. That's free.

The resistance of the MSB pin output makes the step size wrong and makes the sine wave zero cross non-monotonic.

We'll synth an octave of frequency and not ever run at 1 KHz, but runing slow lets us see the waveform steps.

Scoping the bits gets amazing as we get anywhere near Nyquist. One could swear they are all random noise, but they sum into a beautiful sine. Building your own DDS is worth it for the amusement alone.

One eclips gate costs about as much as our FPGA. And 15x as much as our CPU.

The T20 is using about 30 mA of core current, about 40 milliwatts, to run a lot of stuff, including the 250 MHz DDS. Imagine the power and cost of a bunch of ECL flops. And how would you make the ECLs into the sine wave? Use an ECL-input DAC?

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

It was a real pain to Spice this! Actually sort of fun.

The NCO will be 32 or maybe 36 bits. The Efinix likes to do math in 18 bit chunks. The sine lookup table is 12 bits, because it's basically free.

I'm seeing sub-ns period jitter on my scope, and I expect it will be better when the lowpass filter and comparator are all on a pcb.

Here's the proto board. It tested a bunch of stuff.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Ask Mr Google.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

But nasty. Back in 1995 I could buy a 500HMHz crystal controlled oscillator with a 1 psec jitter spec. It wasn't all that cheap.

There are parts that rely on surface acoustic waves that run even faster.They weren't off the shelf parts back then, so I wasn't interested.

That's a remarkably cheap and nasty ADC. Buffer the FPGA outputs with proper switches and even you should be able to do a lot better.

Sometimes it pays to split the MSB over two switches so the non-linearity of the switch resistance is less salient.

But not clearly enough to let you see how to improve them.

You don't have to imagine the power and cost of a bunch of ECLinPs D-type monostables. They have part numbers and data sheets.

An ECL-input DAC would work, but you could use something quite as cheap and nasty as your current improvised DAC, but hanging of the ECL outputs.

What your revelations have made clear is that your problems with your sinewave output aren't due to any kind of timing problem, but rather your choice of a particularly cheap and nasty improvised DAC.

It makes sense to put it in an orbit where it's solar cells can always see the sun, but it's going to be exchanging data with its customers for most of the day, every day.

This seems to be one more case where you have used a phrase that you don't actually understand in an inappropriate context.

Am 05.02.26 um 06:01 schrieb Bill Sloman:

In an ideal world, that costs 20 dB of phase noise for the f*10. The real world is usually worse. I think the ECOC2522 100 MHz oven is at quite a good price/ performance ratio <

From a 2*LVC125 driver you get quite a lot of energy at 300 MHz, just filter it. At 5V5 even more. <

Any ideas for 300 MHz SAW filters that are not unobtainium??

Just the right clock for my LMX2595 synthesizer. <

You can operate an array of these synthesizers with the same settings and the phase noise averages out. The price of the chip sets a natural limit on averaging, however.

You can get whispering gallery mode sapphire oscs as a catalog item from Poseidon Scientific in .au at 10 GHz or so. Size of a shoe box and the price hurts.

In Idar-Oberstein, a town 30 km from here, is the German Gem Museum. When my then lil daughter was still in her princess age, we were often there and watched the pretty rocks. I then meditated what interesting things could be done with one of these huge saphire blocks, when I had the grinding & the cooling problem solved. Factoid: Idar-Oberstein must be the most American town possible, Bruce Willis was born there.

More on timing etc, a bonanza: <

The real problem is that the effective point of the zero crossing jitters by up to 1 clock with 1 LSB amplitude unless you generate an exact subharmonic of the clock. And then it comes from a chip dissipating maybe a Watt on completely unpredictable frequencies and the ground bounce accompanies it.

In Crawford's Frequency synthesizer Design Handbook is a plot that compares ECL, TTL, FACT etc with regard to phase noise. ACT wins hands down. The book predates LVC.

Gerhard

Google some more maybe.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

It's not a nasty ADC. It's a pretty good 6-bit DAC.

That would work. We're paralleling two pins somewhere else. But just changing the MSB resisttor works too. I can't experiment with paralleling because the FPGA is a BGA.

My guys picked some FPFA pins for the MSBs that don't have programmable drive strength, otherwise we could play with that.

I just found a small monoticity problem and fixed it. Maybe I'll FFT the 1KHz sine wave and play with that too. Just for fun: the clock generator looks great already.

My apologies for suggesting that you might ever have any imagination.

I don't have problems. I have a great DDS clock source for under 50 cents. It can be reprogrammed for frequency in nanoseconds, unlike commercial expensive DDS chips with klunky interfaces.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

The DDS and subsequent dividers buy back that noise.

That's about the cost of all the parts on this product. And more power consumption.

This will be the internal trigger option for a pulse generator. Sub-ns RMS jitter will be fine.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

That's not going to make you any more coherent.

Really? Do explain how.

So it is cheap crap. You've just admitted it.

Your ideas about what imagination looks like and how it works are a bit comical. Sensible people don't use their imaginations to find out documented facts.

Sure you do. You want to describe a cheap and nasty version of a DDS clock source as "great". The word would be "adequate" if you haven't missed any other problems it may have.

Most of them are intended to be used with an analog filter on the output and that filter will have a settling time longer than nanoseconds.

I'm using a very simple 50 MHz lowpass filter. That settles in under

An Analog Devices DDS typically has a very pokey SPI interface and costs around $15.

Not many people make DDS chips these days. Maybe just ADI.

I ran an FFT on my sine wave at 10 KHz. The filter has no effect that low. I'm seeing a 2nd harmonic about 20 dB down. Not terrible.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

It's easy to make them in FPGAs.

Considering how crappy your improvised DAC is, 20dB is surprisingly good.

A better DAC should do quite a bit better. Second harmonic distortion is entirely the top half of your sine wave being different from the bottom half. Tuning the most significant bit of your DAC output could probably reduce it dramatically.

It would be big and expensive. My "dac" costs about 5 cents.

Given a 250 MHz clock, risetime/falltime asymmetry could explain some of the -20 spike. What I have so far is plenty good... well under 1 ns p-p jitter on my Rigol scope.

I'll probably wait until it's on the final-product PCB to fine-tune it. I'll have a different lowpass filter and a comparator right there, not the fuzzy sine wave on a 50 ohm scope.

This DDS thing had endless opportunities for tweaking. My FPGA guy did a 12-bit (4096 entry) sine lookup table with 6 bits out. I suppose one could cancel the 2nd harmonic by distorting the lookup table a bit.

This could be a student project for someone.

I thought that making a 50-cent DDS was a cool idea. You obviously don't.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Picosecond delay and width resolution and picosecond jitter are sellable features.

Our DDGs are better than the little pulse generator that we're designing now, but we think there's a place for a less expensive lower-performance 8-channel pulse generator.

Pushing performance to the limits is cool, but it's also interesting to do something simpler and cheaper once in a while. It's a different challenge.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

But you don't seem to be selling them.

True. And a lot less challenging.