Achieving 98% efficiency in a boost converter

You pick tolerance, % loss is the key parameter to study.

Hey, sea moss, I need your exact mailing address, please. My package to you was returned. email: snipped-for-privacy@yahoo.com

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 Thanks, 
    - Win

Received, thanks!

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 Thanks, 
    - Win

To reiterate an announcement: the RIS-767 dropbox folder now includes a searchable assembly file, to find specific parts among the hundreds on the PCB. I imagine you'll not place more parts than are needed for your experiment.

Here, a short rant about the RIS-767 and its test-bed goals: The goal is not to beat some loss value at a certain set of voltages and currents, but rather to do well under some particular sets of conditions you'd like to try. It is called a "test bed" after all.

Some circuitry runs on Vcc=5V, my idea is not to count that current drain. My thinking is that this stuff can be arbitrarily improved later, and made insignificant. In contrast, active power-conversion stuff is where the rubber meets the road, and that's where we're concentrating our attention. Because the switches may be running on 5V or 3.3V, the input voltage can approach 0 volts. That could be interesting. I have a special interest in 600mV and 2.0V.

The output voltage can range up to Vcc, using the current-sense amplifier ICs. If there's no U9, and U12 driver is used, higher output voltages can be tried. My special interest is 2.4 volts.

I have a few of test-set boards left, if anyone wants one.

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 Thanks, 
    - Win

Not infinitely, of course; consider: what's the power gain of a MOSFET? If you keep stacking more and more in parallel, eventually Qg + Rg dissipates more power than the load current does, and your transistor is so oversized, its "power gain" is less than 1 (an odd way to describe gain: that is, output loss over input loss, but it works for efficiency's sake :) ).

By then, you're looking at alternative gate drive methods. You can't improve the Q factor of the gate externally, so you need to use RF transistors, or slower switching speeds (where the Q is good again), and use an inductive kick method to switch the gate voltage while recovering gate energy.

Which, in turn, could be subject to power saving methods, and so on...

One might suppose a telescoping series of these -- which could span quite a few orders of magnitude, all the way down to 20nm -- could save the maximum amount of power.

That'd be pretty crazy...

Tim

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I see all losses only attributed to the effective Q or loss tangent or diss ipation factor in any part at its operating spectrum.

The specs must be defined a priori before any opinions on design review can be seriously applied. Pls define all critical parameters and load impedanc e Z which includes ESR.

Critical specs also inlclude load regulation error , supply regulation erro r and overshoot to a step or pulse load or phase margin and EMI for CM nois e for E field since H field is minuscule from low current,

Considering efficiciency losses of 2% , you must design a budget for Q on e ach part. This ratio of reactance to resistance inversely is related to the passive time constants like ESR*C and DCR/L and RdsOn* Coss and which you want to be much less than the switching period e.g.

Win, thanks for re-sending the board. Assuming I don't get evicted in the next few days we should be okay.

Tim touched on a point I was thinking about. I like the idea of neglecting the power used by control circuitry, but I think it's important to include gate driver consumption as part of the efficiency calculations. Gate char ge is a major player we can't ignore.

Regarding motor-boating, we may use "burst mode" switching to improve effic iency, which is a kind of intentional motor-boating. I'm going to assume f or now that the load, and any bystanders, are not bothered by these oscilla tions.

Well, yes of course you are right. In many cases it's easy to calculate the gate power consumption, perhaps alleviating the need to measure it. But if the gate-driver is buried inside an IC, it's a bit harder. In some cases I managed to add a series resistor to measure this, but in other cases I didn't.

Yes. Burst operation can be used to extend a high efficiency observed at some fairly-high optimum current, to lower currents. That means, concentrate on finding an optimum efficiency point.

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 Thanks, 
    - Win

All good points! But performance can never be better than it is at some optimum operating point, so it's worthwhile to concentrate on finding and optimizing that. In principle, one can always scale the design to move this point. But if a 2% loss can't be achieved under any condition, then that's where we need to concentrate.

I recognize the result won't even be close to being a full-fledged design, but that can come later.

E.g., the inductor losses (core and copper), the synchronous switch losses, and the operating frequency are all in a dangerous dance. Yes, plus the gate-driver loss. So many tradeoffs to play with.

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 Thanks, 
    - Win

I overlooked R67 on the main board, checks Vcc draw on the flip-chips, such as C, G, H and M. In many cases the gate drain is from the Vy output pin and is captured. There's also intervening adapter chip A, with two sense resistors.

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 Thanks, 
    - Win

Have found two errors on the RIS-767 so far (27May):

1) U2, an important switch choice, is fine with TI's ts3a24159dg dual 3.3-volt 0.2-ohm spdt. But the ts5a22362dg dual 5-volt 0.5-ohm spdt is no-go. Awwk, TI swapped the control and NC pins! This also applies to U27 on flip-chip G: ignore the TS5A22362 silk-screen label and use TS3A24159DG.

Haha, ts3a will likely out-perform the ts5a anyway. We may find out, Rob Legg has made cut-jump fixes.

2) U19, the cute 0.5A MAX17222ELT boost-converter, oops, totally wrong pinout, my fault, no excuse.

All the other IC footprint pinouts have passed a double check. My apologies for the errors.

3) Not an error exactly, more a typo, but the node marked PWM on the schematic, which travels all over the place, is actually an inverted logic signal, *PWM. Or fPWM, /PWM, PWM', !PWM, or your choice. (note: R1 and R2 program U1 for inverted-out mode.) 4) My convention, showing switches in their logic-HI position, can be confusing, logic-LO is more common.

Updated schematic (with lots of added annotation), plus an errata page will be posted to dropbox. Labels and U19 will be fixed in the next PCB pass. U27 on flip-chip G2 will be rewired for TS5A22362.

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 Thanks, 
    - Win

Win,

Given the recent results for TS5A22362 and ungapped EP13 choke, might it not be a good idea to generate some kind of formatted standard test report for the RIS767?

This could guide measurement collection procedures/targets, assist in the immediate digestion of collected data and be a step in coordination of results at a later date.

It would have to be pretty extensive, even perhaps going as far as to include standard equipment lists (serial# ? cal date ?) I'm not suggesting a form for recording raw data - that would just be torture.

Sometimes more (iterations) is actually less. You might have to request specific trials.......to either avoid duplication or to attempt it.

It'd also maybe cut down on explanations/justifications required in distribution of 'standard reports' between participants.

Rob Legg

I think that's a great idea! Why don't you make one! You can populate it with your own data as a test case.

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 Thanks, 
    - Win

Without some kind of feedback on where the presented data range and report either succeed or fail, I'd be groping at straws.

More than 75% of my time, so far, has just gone into correlation of shunt and meter readings, permanently-attached instrumentation side effects and control current/board routing influences - and I still couldn't get much output that made sense below 10mA.

I'd hate to have to orchestrate such an ineffective procedure, before the first active measurement trial could start, or account for variations which might arise as more locations were populated, or the board was spun. Hopefully, the board spin can cut down on that nonsense.

The report form needs to be directed towards goals, while providing sufficient trend visualization to allow analysis within and between series of trials. The single source and load condition doesn't even reflect the initial real-world field problem - so aiming at the first without examining conditions that span the two seems a little short sighted. Without an accurate aim ( ie - not a single load condition) you run the risk of having to repeat work for that reason alone.

Output format is heavily influenced by those parameters that can be controlled over the series of measurements. Open loop frequency and duty cycle are provided, though this has to be manually set by eyeballing a scope or trusting another measurement instrument.

It was a real bug-bear providing anything like a constant voltage source. The employment of remote sensing (and multi-turn manual adjustment for manually adjusted hardware) is probably going to be unavoidable.

Setting the output voltage through an internal regulation loop might be useful in a commercial trial, but would be blind to point-of-load conditions that a PV power source rightly expects. An external constant voltage shunt regulator might make more sense, if the remote sensing issues for such a means of regulation can be addressed

I found a constant current load to be invaluable in data cross-referencing, however this suffered from all the usual issues of low voltage operation and control current infection. It is a relatively simple matter converting this to shunt voltage regulation, albeit with the same issues.

In any event, your feedback from any attempt to apply currently collected data to the application issue is essential to reducing waste in subsequent trials. Also, the issue of a board spin is not a small one. The rerouting of power and control ground traces; the reassessment of test measurement point will influence As populating the test bed location and connectorization; the practical tolerances of built-in instrumentation or Arduino capability will all affect the test procedures required to fulfill the purpose of a standard test report.

With single board BOM components running at $70 a pop, the choice to populate a second board or to wait for a respin, will also need your feedback.

RL

The second to last para should read:

In any event, your feedback from any attempt to apply currently collected data to the application issue is essential to reducing waste in subsequent trials. Also, the issue of a board spin is not a small one. The rerouting of power and control ground traces; the reassessment of test measurement point location and connectorization; the practical tolerances of built-in instrumentation or Arduino capability will all affect the test procedures required to fulfill the purpose of a standard test report.

*ing portable PC touchpads....grumble grumble

RL

My idea is restrict my measurements to an appropriate measuring region, not necessarily fully determined by an external goal, but more by the parts at hand. For example if you get best results (hopefully near 98%) with a 50mA load, rather than 10mA, fine! Trying various inductors, different MOSFETs, different frequencies, voltages and currents, etc., is the whole idea of an adjustable "test bed".

The RIS-767 is for low-voltage testing. It's limited to a range of 0.3 to 4V input and up to 5V max output, except for up to 15V out, with certain restrictions.

--
 Thanks, 
    - Win