Acceptable SSR switching patterns for mains heater

Nov 26, 2006 4 Replies

Hello,



I need to regulate a 220V resistive heater with a Solid State Relay. The heater power is a few kW. The SSR is of a type that only switches on or off during zero crossings (which is fine, because I want to minimize interference).



I'm switching the SSR with a microcontroller. I have an opto coupler attached to the mains, so the microcontroller can detect the phase and frequency, and control the SSR in sync with the mains.



My goal is to control the heater output as smoothly as possible. I want to do this by switching by half-period intervals, but I am wondering which switching patterns are considered acceptable for (power company) transformers.



For instance, a 50% duty cycle can be created by this waveform:



_ _ _ / \\ ______/ \\ ______/ \\ \\_/ \\_/ \\_/



But also by this one:



_ _ _ ___/ \\___/ \\___/ \\___



However, the second pattern, which only uses positive half periods, results in a DC current, and I understand this can cause losses in the transformer.



Now, I'm wondering about this pattern, for a 75% duty cycle:



_ _ _ ___ / \\___/ \\ / \\ \\_/ \\_/ \\_/



Would that be acceptable ? I assume so, since there's no DC component. Or this one for a 25% duty-cycle, which has a DC component, but it's relatively small:



_ _ ___/ \\_________/ \\______


Basically, I'm looking a simple guideline as to which patterns are considered acceptable, and still get the most switching flexibility. Or do I need to worry at all ?



If your system has the intelligence to avoid DC, completely, do it. The distribution transformers will also like you better if you don't hit the same polarity of half cycles twice in a row, even if you balance the DC out, eventually.

The more evenly distributed your power pulses are, the less annoying light flicker other users of the line will experience. You might use every third half cycle for 33% power, every 5th for 1/5th power, etc., instead of every third cycle or every 5th cycle. For 1/2 power, I think every other cycle is as good as you can do, but for 1/4 power you can use every 4th cycle, or a positive half cycle, a skipped full cycle, a negative half cycle, and two skipped cycles.

Thanks. So would you suggest that for 3/4 power it's better to use 3 full cycles, followed by an idle cycle, rather than the pattern I had in mind (which had two positive half cycles in a row) ?

It's not hard to implement. I'm basically using a delta-sigma modulator, extended with a small state machine that keeps track of previous actions. If a certain pattern is not allowed, it will skip a pulse, letting the integrator add up the error, and compensate it later.

It seems that a simple rule that enforces alternate polarity for each pulse would produce the behaviour you've suggested.

I would.

I think so.

...

You might try some of these links:

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Have Fun! Rich

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