A strange problem with CMOS Up/Down counter

I would check the clock polarity. Make sure that the unused one is not left in its active state when clocking.

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Luhan Monat (luhanis \'at\' yahoo \'dot\' com)
"The future is not what it used to be..."

Yo.

Something strikes me as odd about your description that may help sort this out, (assuming Mr. Monat's comments don't do it).

What is the difference between the count 2 to count 3 transition during your step 1 and what should be the same transition during your step 2 or step 3? If the problem is repeatable, there must be some difference in conditions, either in the intended logic inputs or in some unintended input arising from cabling, the way the circuit is wired, interference, or ... something. So, what is it? The answer will be telling.

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--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com

one

What are you using for the clock signal? If you have pull-ups on the clock line, how big are they? I've had strange results like this when the rise time was too slow on the clock.

Thanks so much for the replies.

Luhan Monat: I checked the clock polarity. The "down" clock stays as it should.

Larry Brasfield: Indeed, this observation is very perculiar. Yes, problem is definitely repeatable. Somehow it appears to me that the IC knows whether I am starting from 0 to 1 to 2 and so on. But whenever I count from 3 to 2 and try to count back to 3, it won't allow me to do so unless I double clock it. I tested everything. I checked everything. Just doesn't make sense.

Anthony Fremont: I am using a tactile switch. I used a 10k resistor and

1uF capacitor. Thing is regardless of the size of the resistor or capacitor, this problem is still there. But you brought up an interesting point. So, if rise time is slow, it will take two "clicks" to swich from 2 to 3 instead of one click? But why is it that it only happens from 2 to 3?

I want to add another observation...

Counting from 1 to 3 back to 2. At this point, if I click down to 1, it's ok. Then count from 1 to 2 to 3. It's ok.

and

My experience was with a serial shift register. Every thing worked good until I clocked in a 0 bit, then all the outputs would reset simultaneously. You could try using a Schmitt trigger inverter to square up your clock signal and see if that helps.

Anthony, thanks for the follow up.

I solved the issue this morning by adding a 0.15uF to the clock up input and ground it. And now the "2 to 3" issue gone. Was there too much noise?

According to the TI datasheet, the maximum clock rise or fall time is

15us. Thus, your clock is far too slow. A 1uF cap + 10k resistor has a tau of 1/100. That means it is about 1000 times too slow. There is some wacky arbitration circuitry to protect against races between the clocks which could be getting you.

Regards, Bob Monsen

Unbelievable !!CRAP!! "What is it?"- that's what he's asking you, stupid? And as usual, all anyone gets is a bunch of verbose gibberish. If you don't know what you're doing then just stay the hell out of the thread, you are a worthless jackass pseudo-intellectual.