6 bit things

Names?

I can get 10 Gbit SFPs cheap, so channel rate isn't an issue. But we need DC balance and circuit simplicity. The new 4-bit thing looks good, 1 0 d \d per frame.

Step-index multimode can be as bad as 20 ns/km iirc. Good graded-index fibre is more than a factor of 10 better (400 MHz * km is a number I've seen).

Single-mode fibre is good for a really long distance--it's just the optical bandwidth that sets the dispersion.

Cheers

Phil Hobbs

Right. Multimode has bad time dispersion.

The Guinness record for an un-repeatered fiber link is 10,358.16 km.

I'd assume that you would prefer not to do that.

If both zero and one MDATA samples are each coded with a DC balanced pattern, there is no need to restrict the voltage range.

This MDATA signal seems to be pulse-width modulated,not sigma-delta (despite the name), sampled at the ADC clock rate. What is being transmitted is in fact an absolute voltage value, with some quantization noise added. See datasheet page 16.

No idea why they talk of sigma-delta. Certainly was confusing me.

Maybe the sigma-delta stuff is buried in the front half of the "ADC". There was talk of an internal 16-bit register somewhere. It could be accumulating the up/down change pulses, the current value of this register being what is pulse-width modulated and transmitted back to earth.

Yes. Basically, what we are discussing here is how long the symbol pattern should be. You still need a way to decode that isn't vulnerable to frame-shift errors.

For which you need long strings of either kind of symbol (zero or one) to decode in exactly one way, not using the end of one symbol and the start of the next to declare an ADC sample. So the pattern cannot be too short or too simple.

Digital correlation receivers are pretty simple, basically a shift register with outputs being summed, half being direct and half being inverted.

When the sought-for pattern is centered in the shift register, the summer emits a peak of amplitude N. Otherwise, the output amplitude is roughly zero, max unity, where N is the length of the pattern (and thus shift register) in bits. No computer needed.

If they all claim the enet PHY mentioned later, the AGC time constant ought to be about the same, most likely being specified in the relevant enet standard, to ensure that SFP modules are interchangeable.

Singlemode fiber is cheap, and will certainly do the job. The Ethernet PHY you want for this is "1000BASE-LX", as defined in IEEE

Going one-fifth the max reach should yield ample optical SNR, so long ate there are few optical connectors

Joe Gwinn

Yes. It turns out that the max reach is one km, and singlemode will go five km.

It should, but the two-bit and four-bit schemes may be challenged. And also suffer from framing errors.

At 50 meters, basically anything will work.

With signals sent by RS422 over wire, the standard observation/joke was that one could sent this signal on a two-strand barbed wire fence

-- so long as the cows didn't use the fence as a back scratchier.

Joe Gwinn

Biphase-M code (FM) does that for 2 slots per data bit instead of 4

It seems like you're reinventing the wheel, and having rejected the triangular wheel for the square wheel are impressed by the improvement it gives.

Well, at least a Reuleux Triangle rolls with constant width!

Oh! You're right! Thanks.

That, for some weird reason, reminds me of a DDS frequency synthesizer variant that we invented on Friday. Maybe I'll post that and see how much hostility that one inspires.

Or you can use Manchester encoding to encode the clock and easily recover it at the other end. Data bits with the clock for free! I guess some people don't like free.

You could send the bit and its 1's complement right after for less than half the cost.

How would the receiver distinguish between a stream of 1s and a stream of 0s? They look alike.

lørdag den 13. august 2022 kl. 05.17.29 UTC+2 skrev John Larkin:

you can't, but since it is a DSM stream you'll have lot of transitions unless something is wrong so it could still work since 00 means the data changed from 1 to 0 and 11 means data changed from 0 to 1

Version 4 SHEET 1 3268 680 WIRE -544 -448 -592 -448 WIRE -544 -352 -544 -368 WIRE 2160 -304 2080 -304 WIRE 2160 -288 2112 -288 WIRE 2496 -288 2224 -288 WIRE -592 -256 -592 -448 WIRE -416 -256 -592 -256 WIRE -192 -256 -256 -256 WIRE 528 -256 -192 -256 WIRE 560 -256 528 -256 WIRE -416 -208 -464 -208 WIRE -464 -144 -464 -208 WIRE 368 -144 -464 -144 WIRE 400 -144 368 -144 WIRE 2160 -144 2064 -144 WIRE 2160 -128 2128 -128 WIRE 2368 -128 2224 -128 WIRE 416 -112 96 -112 WIRE 1712 -112 1648 -112 WIRE 368 -96 368 -144 WIRE 432 -96 368 -96 WIRE 96 -32 96 -112 WIRE 160 -32 96 -32 WIRE 368 -32 368 -96 WIRE 368 -32 320 -32 WIRE 2128 0 2128 -128 WIRE 2352 0 2128 0 WIRE 160 16 80 16 WIRE 416 16 416 -112 WIRE 416 16 336 16 WIRE 2112 48 2112 -288 WIRE 2320 48 2112 48 WIRE 2624 64 2384 64 WIRE 1648 80 1648 -112 WIRE 2624 96 2624 64 WIRE 2880 96 2624 96 WIRE 2496 112 2496 -288 WIRE 528 144 528 -256 WIRE 656 144 528 144 WIRE 432 160 432 -96 WIRE 656 160 432 160 WIRE 864 160 752 160 WIRE 1216 160 1024 160 WIRE 1648 160 1280 160 WIRE 1888 160 1648 160 WIRE 2080 160 2080 -304 WIRE 2080 160 2048 160 WIRE 2128 160 2080 160 WIRE 2320 160 2320 48 WIRE 2320 160 2288 160 WIRE 2384 160 2384 64 WIRE 2416 160 2384 160 WIRE 2624 160 2624 96 WIRE 2624 160 2576 160 WIRE 752 192 752 160 WIRE 752 192 736 192 WIRE 864 208 800 208 WIRE 1888 208 1840 208 WIRE 2064 208 2064 -144 WIRE 2128 208 2096 208 WIRE 2352 208 2352 0 WIRE 2352 208 2304 208 WIRE 2416 208 2400 208 WIRE 80 288 80 16 WIRE 800 288 800 208 WIRE 800 288 80 288 WIRE 80 304 80 288 WIRE 1840 320 1840 208 WIRE 2096 320 2096 208 WIRE 2096 320 1840 320 WIRE 2400 320 2400 208 WIRE 2400 320 2096 320 WIRE 2368 352 2368 -128 WIRE 2496 352 2496 256 WIRE 2496 352 2368 352 FLAG 80 384 0 FLAG -544 -352 0 FLAG 1840 400 0 FLAG 1712 -32 0 FLAG 400 -144 ADC_CLK FLAG -192 -256 ADC_Dp FLAG 2880 96 DATA_OUT FLAG 560 -256 MDATA SYMBOL voltage 80 288 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value SINE(.5 .5 80e6) SYMBOL bv -544 -464 R0 WINDOW 3 52 61 Left 2 SYMATTR Value V=RAND(time*1e8) SYMATTR InstName B1 SYMBOL Digital\\dflop 240 -80 R0 WINDOW 3 8 12 Left 2 SYMATTR Value td=1n SYMATTR InstName A2 SYMBOL Digital\\dflop -336 -304 R0 WINDOW 3 8 12 Left 2 SYMATTR Value td=1n SYMATTR InstName A3 SYMBOL Digital\\dflop 944 112 R0 WINDOW 3 8 12 Left 2 SYMATTR Value td=1n SYMATTR InstName A4 SYMBOL Digital\\dflop 1968 112 R0 WINDOW 3 8 12 Left 2 SYMATTR Value td=1n SYMATTR InstName A8 SYMBOL Digital\\dflop 2208 112 R0 WINDOW 3 8 12 Left 2 SYMATTR Value td=1n SYMATTR InstName A9 SYMBOL Digital\\dflop 2496 112 R0 WINDOW 3 8 12 Left 2 SYMATTR Value td=1n SYMATTR InstName A10 SYMBOL voltage 1840 304 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value SINE(.5 .5 80e6 200n 0) SYMBOL cap 1280 144 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 10p SYMBOL voltage 1712 -128 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value 0.5 SYMBOL res 1632 64 R0 SYMATTR InstName R2 SYMATTR Value 1k SYMBOL Digital\\xor 704 112 R0 SYMATTR InstName A1 SYMBOL Digital\\and 2192 -336 R0 SYMATTR InstName A5 SYMBOL Digital\\and 2192 -176 R0 SYMATTR InstName A6 TEXT 1200 -504 Left 2 !.tran 1u TEXT -400 -472 Left 2 ;ADC sim TEXT 880 -440 Left 2 ;Transmitter TEXT 1480 -448 Left 2 ;Reciever TEXT 2288 -304 Left 2 ;11 = 0->1 TEXT 2288 -152 Left 2 ;00= 1->0 RECTANGLE Normal 1088 432 -64 -496 2 RECTANGLE Normal -624 -496 -144 -144 2 RECTANGLE Normal 3040 432 1440 -496 2

You'd need a sync pattern for start of frame, 16 zeros followed by 16 ones, say. Maybe 4 instead of 16.

then just 10,01,01,10... an agreed number of times.

Might ECC it; Hamming, others. It's optical so maybe a YAGNI.

Wild arse guess is 50 lines of C for the encoder and 50 more for the decoder ( sans ECC ) . Maybe a smidge more for operating a DMA or two.

PIC16 might be big enough. Should be close to bit times in latency.

Bits are always paired as 01 or 10, meaning 0 and 1 respectively.

yes so every time there's a change in data you get a 00 or 11 in the stream

eg data = 00101100 -> stream = 01.01:10:01:10.10:01.01

with 20MHz data rate?

My premise was that I'd build both ends with no code, no c and no VHDL. Just small-scale cmos logic chips.

And I want to ship 20 Mbps, kinda fast for 50 lines of c.

I guess that biphase, 01 and 10 with detection of 11 as a bit framing error, could be done with a bit of discrete logic. A delta-sigma adc would provide lots of opportunities to test that.

søndag den 14. august 2022 kl. 15.33.00 UTC+2 skrev snipped-for-privacy@highlandsniptechnology.com:

not need to mess with frames, just one flop, if you see 11 set the output, if you see 00 clear the output else leave it as is

I guess you didn't see the spice sim