6 bit things

There's no point in a challenge to design the worst CPU architecture, since it's been done so many times already.

The ADUM7703 can be clocked up to 20 MHz, but we really don't need to do that. 10M would be plenty.

Some customer's analog voltage. Might be a strain gage load cell, for example. We'd have some input ranges.

Neither, actually. I just want to transport the ADC output correctly.

The ADC has a one-bit output over +-320 mV input, and averages 50% duty cycle at 0 volts in. I just want to transport that bit over a fiber link.

I don't want an FPGA or a uP in this box. All my coder-people are too busy on other projects now. So, a few gates and flipflops.

Manchester encoding is one of the simplest things in the world to decode. It's also very easy to encode. Look it up. You'll be surprised at how easy it is.

The refrain was seven words actually, so not DC balanced.

no, this is why internet standards use the term "Octet" instead

sixpence? Nintendo called 5 bits of their 10 bit word a nickel. "Sextet" would work also.

looks like manchester encoded one bit PWM

seems heavy on clock and light on data. I'd call that a symbol.

Is there a better term for the code used to control WS2812 leds than one bit PWM?

You can always add more bookshelves...

My friend and I got Volume I Fundamental Algorithms as undergraduates and worked through most of the problems including implementing a virtual Mix machine. We even found a bug in the prime number test example and sent it off hoping for 2^N dollars in return. It had already been reported so we just got a nice postcard back from him instead.

Someone borrowed my copy of Seminumerical Algorithms and never gave it back. I never did get to Sorting and Searching (my friend did).

LaTex markup language remains as one of the side effects of Knuth finding no suitable markup language for such documents.

ISTR Roff on Unix or the IBM mainframe was the least unsuitable option at the time and later something odd and nearly Wysiwyg (but not quite) from Manchester University running on a Sirius PC as a word processor.

A byte with 2 null bits...

I think Leslie Lamport deserves a bit of a shout for LaTeX :-)

I was quite attracted to Knuth's literate programming ideas for a while, but in multi programmer projects the approach was allways rejected.

You can't deny that LaTeX makes beautiful documents, and it will never trash your source files, contrary to some other piece of $oftware we all love to hate. It sure is weird though.

And don't believe the statement that you can concentrate on contents and forget about the formatting. Still, it's my first choice for slides and text documents, if the choice is mine.

Jeroen Belleman

All very low bandwidth stuff. Is it required to transmit absolute values, or is just the "AC" part enough?

Sounds like for instance actual strain values are desired.

OK.

So the ADC output is a signed bit per sample.

OK. This too can be done, given a large ratio between optical bit rate and ADC bitrate.

The AGC in the SFP is pretty fast, but the optical bitrate must be much faster, or the AGC will flatten the desired signal. The SFP datasheet should define the AGC response speed.

So, pick a convenient optical signaling (flash) rate well above the AGC reaction speed, so you will be able to recover the sent pattern at the SFP output.

Here is one possible design:

Choose a ADC sample rate a fraction of the optical rate. The fraction is determined by choosing orthogonal codes to represent +1, zero, or

-1 ADC outputs to be sent. Also need a frame-start symbol.

The orthogonal codes are chosen from the standard Gold Codes:

.

The codes have odd length, and are fairly close to balanced, so one ought to be able to find some truncated Gold codes of even length (drop last bit) that are exactly balanced. We need only four such symbol codes, and a 16-bit code would allow the optical rate to be 16 times the code (ADC output) rate.

There must be a steady stream of ADC symbols, even if ADC output is zero, to keep the SFP AGC stable.

Generation. Drive a 16-line demux with the optical clock. Make or don't make connections from the demux to an adder, as dictated by the symbol to be sent. The adder output is used to drive the SFP TX input.

Reception. Lock a phase-lock loop to the optical flash rate, to recover the optical clock.

Have one correlator per symbol type, all running in parallel. Given the near-perfect correlation behavior of Gold codes, the correlator output will be roughly one unit amplitude except at the pattern center, where the peak will be about 16 units, so a threshold set at 8 units should enable perfect recovery.

The frame sync symbol is used if we are switching between a reference voltage and the strain-gage output voltage, to mark where reference starts. May need an ref-end symbol.

If no correlator peaks for more than a few symbol periods, complain. The SFP will also tell you if any optical power is being received, if I recall.

Design the receiver first, as it's usually the harder of the two, then design the transmitter to make the receiver happy.

Joe Gwinn

The difficulty with literate programming is that you need to find literate programmers.

Modern programming languages tend to assist the programmer to reveal their intentions to a much greater degree that was e.g. the FORTRAN in which Knuth wrote TeX.

But programmers still have to have a sense of which things might or might not be already known or become apparent to another human - meaning they need to see outside their own heads. That's not very common, and even less so in more productive programmers.

It's an ADUM7703 delta-sigma a/d converter; it doesn't actually sample but runs its stuff continuously. It has a clock input and a single bit logic output. The duty cycle of the output reports the analog input:

The combination of AGC and AC coupling makes SFPs not work well at data rates below about 1 MHz. That varies a lot with specific parts.

It's really simple; just move the 1-bit logic level output of the ADC to the destination and recover a clock to know where the bits are. We'd clock the ADC at 20 or maybe 10 MHz.

Nah, two bits is a quarter, so 8 bits is a dollar.

Cheers

Phil Hobbs

The fact that the ADUM7703 is clocked implies that is samples on the clock. Otherwise, why require a clock input? Datasheet page 4 shows the relationship.

More at end.

If I'm understanding the timing diagram on datasheet page 4, one can have a long string of ones, or of zeros, depending on the input analog voltage, which has fairly low bandwidth and so can linger at a voltage for very long durations.

It's these long rafts of ones or zeros that I worry will baffle the SFP's AGC function, causing data-dependent link failures.

What make and model of SFP are you looking at?

But one could use two Gold-code symbols, encoding MDATA one and MDATA zero, and a pair of correlators at the other end of the fiber-optic link to recover the original MDATA stream.

And, optical SNR matters. If the minimum SNR is high, the tolerance for non-zero DC balance, is increased. What is the maximum optical cable length contemplated?

Joe Gwinn

Since you are transferring only a single (net) bit, why are you worrying about the names of the actual frame bits ?

Compare to the situation with asynchronous serial communication. A UART can usually transfer 5-8 (some up to 14) net data bits, but in addition to this, the start bit is added, an optional parity bit and

With optical fibre losses of a few tenths of a dB/km and a likely link margin of well over 10dB I don't think optical cable length will be an issue here. The originally proposed 6-bit encoding scheme included the data bit followed by its complement, so that will have removed any dc baseline fluctuation issues. SFPs are remarkable tolerant of optical abuse. I have tried using multimode fibre with single mode SFPs and single mode SFPs with multimode fibre over lengths of around 50m at 1 and 10Gbit/s. Every combination works fine despite the optical losses in some of those configurations.

John

Of course voltages near the negative rail have to get close to 0% duty cycle, low bit density. I can avoid that by not allowing more than, say, +-250 mV.

Delta-sigma "noise shapes" to push the data spectrum up, namely avoid low frequency components in the duty cycle.

That's the reason to send 4 bits for every actual payload bit, to keep the SFP data balanced.

I've evaluated a bunch of them. I'll have to look that up.

A couple of km, maybe. Singlemode can go 10s of km.