What does that clock input look like? I can't imaging it is a TTL level input. What are the thresholds? Perhaps an opamp to boost the signal and capacitor coupling it into the clock input which is biased around it's threshold might do the trick. This also ensures a 50% duty cycle.
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Well, "You have mismanaged your component configuration" sounded sorta personal to me. Last design we did - just shipped the first units a couple weeks ago - we had more level shifter chips on the board than logic chips.
John
It's not an insult, it is an observation that it is kind of dumb to set a requirement that cannot be met by existing logic technology- somebody was not thinking.
We're using the TI 74ALVC164245. Nice part... 16 bits in each direction. Philips and IDT make it, too. Pericom may have an equivalent, but their web site is so bad it's hard to tell.
Just when things were settling down, now we have to cope with lots of different logic levels.
A tuned circuit might work, but it sounds like he may not have enough power to drive the cmos with a passive matcher of some sort.
John
If Pericom doesn't make it, it doesn't exist. Besides, you're in left field if this is a narrow band application- a simple LC does it-and with zero bias current overhead.
Isn't that something to sort out first? For the (space constrained) design I'm working on now, one of the first things I did was eliminating the need for logic level converters. Makes live a whole lot easier.
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Fine if you can do it. My board has a VME interface (5 volts, high current), a 5-volt microprocessor (the 3.3 volt version is too slow), a huge Xilinx BGA (3.3 i/o, 1.8 core) and a lot of big static ram (3.3, luckily). Plus a lot of fast DACs, clocks, a PLL, and sundry stuff. You can't always buy everything at the same levels. I think the next gen of FPGAs may only do 2.5 i/o.
John
One of the reasons I rarely post questions to forums like this is that most people are so damn judgmental. Instead of getting pointed responses to a pointed question you get a bunch of "Why the hell did you do this?" or "Any idiot knows you can't do that ...", and a ton of "I would have done this instead ...". Then I have to fight the urge to waste time trying to explain myself, when I know that no explanation will appease the know-it-alls. Thanks to John Larkin for giving me good ideas without questioning why I need to do what I'm doing.
Rob
Hey, Fred, how many new designs did you finish last year? And how much did they sell for?
John
While there is some judgmental comment, I think some is more constructive. To give a professional answer to a question, it is advisable to know as much as possible about the problem, and initial statements of problems are very often incomplete.
Besides, it's only human nature to ask, **sympathetically**, how you came to paint yourself (or be painted by the management) into that particular corner.
-- Regards, John Woodgate, OOO - Own Opinions Only. The good news is that nothing is compulsory. The bad news is that everything is prohibited. http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk
His ideas are shit and you're an idiot.
500MHz is the limit on internal CMOS circuits? Is that really what you mean Jim?! We're better than that on external "busses" and some decent multiple of that on internal logic, five or more levels deep. ....all CMOS.
-- Keith
Hahah- every single one I was "forced" to work on. I don't work nearly as hard as you do- there is no incentive, and sales are an irrelevant consideration.
On Sun, 2 Jan 2005 19:11:24 +0000, John Woodgate wroth:
After pulling Joe out of the river where he was doing a passable imitation of a boat anchor, Bill asked, "How'd you come to fall in?"
Joe replied, "I didn't come to fall in, I came to go fishing!"
Jim
What is too slow?
You can have the Xilinx use different I/O levels for different banks (groups of I/O lines).
Even the newer Xilinx devices like the spartan 3 can do I/O up to
3.3V.-- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nl
The best answer to a question is asking why the question is raised in the first place. Makes people think again about what they are doing, hopefully from a different perspective.
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No, his problem is that he needs a 3.3 volt clock at 600 MHz. I suggested an LVDS-to-LVTTL converter. They act like comparators with screaming fast edges, but the ones I tried wouldn't work well above
300. All-LVDS chips are a lot faster.
An ERA-5 will swing almost 3v p-p into an unterminated line, and over
4 if you shift the bias by pulling the input down a bit. Nice pulse amp.John
I'm surprised you say that about LVDS - I've used FPGA LVDS outputs at 600MHz with no problems. Waveform was very clean, except for about 100psec timing difference between positive and negative transitions.
If LVDS is not an option for the OP, then the MMIC suggestion you made would be the simplest way - keep the impedance level at 50 ohms, it makes things a lot easier, use controlled impedance lines and make sure it is terminated properly.
Regards Ian
Ian -
What FPGA family has that kind of LVDS output performance? Are you talking about 600MHz clock or data outputs? Virtex-2 runs out of gas at around
400MHz for LVDS clock outputs (i.e., 800MHz data). I'd be really surprised to hear that a Xilinx competitor can do 50% better than that.Rob
Not Ian, nevertheless. There are very fast FPGA families, such as the Altera Mercury, Altera Stratix, Altera StratixGX, the last having 3.125 GBit transceivers.
The point is less in having the fast transceivers, than the lower gate count.
Rene
-- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
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