32kHz crystal issues

I'm working on a circuit with a RTC that uses the ubiquitous 32768 Hz crystal. I'm assuming my problems at the moment are due to using a solderless breadboard and not a properly laid out circuit board, but just in case I'm missing something obvious...

My RTC is running a little fast (8%!). I'm pretty sure it's picking up glitches from nearby wires (no ground ring, etc), and there are some step pulses on the sine wave which confirm this. But could someone verify the signals otherwise? The IC's drive signal is 1v peak, but not a sine wave - it's clipped to ground for about 30% of its phase, and has a faster drop than rise. The drive signal after the 330K is a 0.8vpp (0v-0.8v) sine wave. The return signal is a

0.5vPP sine wave centered at 0.8v. Do these sound right? I'd rather at least get this part right before having a board made.

The circuit is an ECS-1x5 crystal, 330K series R, 15pF caps, into a microchip PIC24F (3.3v). The load's a little off (8.5 vs 8 pF) but that's as close as I can get with the caps at hand.

Would a crystal that needs higher load caps be more noise-immune? I seem to get that opinion from various readings.

Would adding 50R resistors to the pins near the crystal help any, assuming I've done the usual ground ring and keepouts?

Thanks, DJ

Reply to
DJ Delorie
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it might be best to have the 330k/xtal node soldered and left flaoting in the air.

1v peak seems quite low for the drive signal.

can you determine the frequency on your scope ? if its realy 8% fast then its probably not running at the crystal resonance, if you took the crystal out it would probably still oscillate.

maybe try larger caps either side of the crystal, and put lots of ground wires, and supply caps.

keep the crystal realy close to the oscillator IC it might help if you can keep the crystal leads either side of a ground conaction. and the same for the 330k.

for prototype board work it might be easier to get a 32khz oscillator module.

ive found the 32khz crystals surprisingly difficult to get to osccillate at times, its becuase the impedance is so high. its far easier to get a 10mhz to oscillate.

COlin =^.^=

Reply to
colin

The added capacitances are likely preventing it from working right. You may also have too long of wires.

This could be normal. It depends a lot on the sort of RTC chip. For CMOS ones the ideal is a slight clipping at both ends of the swing.

Try bending the leads up in the air and soldering short legs together to make something more like the PCB will really be.

It is sort of true. The terminal impedance will be lower so electrostatic signals will have a harder time getting in. On the other hand, there is a point where the Q is the highest. The higher the Q the greater the slope of the phase curve.

The 50R isn't likely to help much unless the lines in question are long.

Reply to
MooseFET

The crystal, caps, and resistor are all soldered onto a tiny PCB with three pins - ground and the two that go to the IC.

formatting link

The spec warns to keep the drive signal under 1 uW, though.

I hooked up my logic analyzer and averaged 10 cycles, it's really close. Hard to be exact because it's not a digital signal, but it says 32789 and that's within the measurement accuracy.

Yeah, the other two crystals are running fine (14MHz and 25MHz) on similar adapters.

Reply to
DJ Delorie

I nearly suggested something like that, you could try a few diffrent crystals, ive found fualty crystals before now, dont get them too hot while soldering, a mistake I made thinking they wernt semiconductors so wertn so susceptable to heat.

however I think the problem might be the inter pin capacitance between the IC leads wich might be 10-30pf due to the breadboard.

maybe you could bend the ic legs up and solder that little board directly, or at least the oscin pin.

Colin =^.^=

Reply to
colin

I'm not worried about accuracy in the breadboard, I'm worried about accuracy in the final PCB. So I guess so far I'm doing everything right circuit-wise, so I'll leave it for now.

Reply to
DJ Delorie

All the bushwa about "added capacitance" making the sucker pull off frequency neatly forgets one small item ... added capacitance will LOWER the frequency, and yours is too high. 32 kHz crystals are quite well behaved once you understand the circuit that you are using them in.

Jim

-- "Life is not a journey to the grave with the intention of arriving safely in a pretty and well preserved body, but rather to skid in broadside, thoroughly used up, totally worn out, with chocolate in one hand and wine in the other, loudly proclaiming 'WOO HOO What a Ride!'"

--Unknown

Reply to
RST Engineering (jw)

the added capacitance is also bypassing the crystal thereby allowing high frequency stuff through. wich looks like its showing in the form of glitches.

8% is far too much to be just 'pulled' anyway.

Colin =^.^=

Reply to
colin

messagenews: snipped-for-privacy@news.supernews.com...

Agreed--the oscillator is *not* crystal-controlled. Your solderless breadboard is horrible(!), but you might at least gap the crystal leads two spaces and ground the center conductor strip to reduce breadboard capacitance shunting across the crystal.

breadboard .-----------. | o o o o o-------------+ | : | | : | | : ------- | : .-----. | o o o o o-----+ | | | : | '-----' | : --- ------- | : GND | | : | | o o o o o--------------+ '-----------'

Another point: the input node is very high impedance--the waveform's easily wrecked by probing. I'd suggest a 22M resistor in series with the 'scope, or ideally, use a FET probe.

Cheers! James Arthur

Reply to
James Arthur

To respond directly to your questions... Get the circuit right and you shouldn't need to change load caps, and with a 330K ESR crystal I can't imagine 50R series resistors doing anything at all.

I'd suspect layout.

Glitches on the input pin might be due to probing. If they show up on the clock's drive pin, that's a problem!

Idea: you could bend up and air-wire the clock pins, or use the shielding tactic I suggested before. If you do this and the problem

*changes*--even if not perfect--you're on the right track.

Cheers, James Arthur

Reply to
James Arthur

That DC offset on OSC2 looks very suspect and worth investigation to find out why.

It could be due to the overall Gain being too large. Try increasing the 330k resistor.

A second possibility is that there is a positive leakage current into the OSC1 terminal.

A slightly attenuated and low pass filtered version of OSC2, still with that suspect offset towards 0v.

The scope probe input impedance might be affecting the DC and AC levels there.

Did you use two scope probes..... one permanently on OSC2 to see what happened when the other probe loaded the OSC1 terminal?

With a 3.3V supply the transition point of the OSC1 terminal should be 1.6Vdc and yet it is still managing to oscillate when down at 0.8Vdc average?

That could be due to excess Gain.

If OSC1 is down at 0.8Vdc average (when loaded) then another scope probe on OSC2 should show that the output signal has moved away from the negative offset, to a large positive offset. Does it?

--
Tony Williams.
Reply to
Tony Williams

!\\ ----! o-------+-----+--- Out ! !/ ! ! ! \\ --- Stray capacitance ! / --- ! \\ ! ! !-! ! ! +---! !-----+--+----- ! !-! ! --- --- --- --- ! ! GND GND

The stray here will push the running frequency up. From my experience, 80 Hz is a long way for a 32KHz crystal to get bent by any external circuit but I assume the OP sees what he sees.

Reply to
MooseFET

Crystals typically have spurious modes, and yours may be oscillating on one of these. Try one of these : use a different brand of crystal, reduce the gain, put a 32 KHz tuned circuit somewhere in the feedback loop.

Tam

Reply to
Tam/WB2TT

Some reminders:

  • The load capacitance is what the spec says it should be, mostly. Not changing that.

  • I asked about using a *different* crystal that needs a higher load cap, but still what *its* spec requires.

  • The scope clearly shows digital glitches on the sine wave, which I'm pretty sure is the cause of the 8% speedup - some glitches cause extra clocks.

I'm not worried about the glitches on the protoboard, I don't think there's anything I can do about those - it's a *protoboard*. The final circuit will be on a 4 layer PCB with proper EMI etc.

I'm mostly wanting to make sure the design will work on the PCB. That boils down to three questions:

  1. Am I calculating the load caps right? If the spec says "8pF" and the crystal is 1pF, I need 7pF*2 = 14pF capacitors each?

  1. Is the 330k resistor the right value? How do I calculate the right value for that specific crystal, given the OSC2 sine wave and 1uW power?

  2. Are there other design issues I haven't mentioned, that I'd need to be aware of when laying out the PCB? I know about the guard ring and the keep outs, anything else?
Reply to
DJ Delorie

Right, the 8% is way outside the spec. It's caused by the digital glitches, I'm almost positive.

Reply to
DJ Delorie

Unfortunately, the pic is a DIP and has the osc pins on adjacent pins (see photo posted earlier). Without bending the pins up (don't want to risk the chip just yet), that's the limit of what I can do. One alternative is to reallocate the pin adjacent to the OSC pins, and ground that pin to provide a wider ground ring around the oscillator.

I'm using the 10x setting, which is the best I've got at the moment. I'll see what I've got for high value resistors.

Reply to
DJ Delorie

I'll try that...

Adding probes doesn't seem to change the waveforms, either way.

I put the second probe on the pin next to the OSC input, and the glitches in the sine wave correspond to digital pulses on the other pin. Could they be capacitively coupled through the proto board? I'm measuring about 2pF between rows. If so, moving that signal and grounding the old pin should fix it, yes? The pin on the other side is Vss already.

Another vote for a bigger resistor.

Nope. No change on either signal, when the other one is probed.

Reply to
DJ Delorie

On Thu, 12 Jul 2007 11:46:52 -0400, DJ Delorie wrote: ...

When the spec says "8 pF", it means that the cap should have 8 pF in parallel with it, including the capacitance of the input pins and strays.

That depends more on the chip than on the crystal - the crystal is involved in that the R value probably sets the drive level, kind of like a feedback resistor. If the spec says 330k, I'd start with that.

As much ground plane as you can put on the board; billions and billions of bypass caps. ;-)

Cheers! Rich

Reply to
Rich Grise

10x isn't usually good enough, as the input impedance can easily be 20 megohms or greater. The 10x probe is then a very heavy load at d.c., dragging down the bias point, and has a capacitance several times your load capacitors, upsetting the loop gain.

Your report on doing Tony Williams' test (loading the oscillator's input node while viewing its output node) kind of rules out these worries though, so onward and upward!

Stray Capacitance Shunting the Crystal You can easily bend up a pin non-destructively. If you're feeling brave you could eliminate shunt capacitance worries by just bending up pin 11 and air-wiring that (Ken Smith recommended the same too).

Other Possibilities It would be useful to know whether: a) the oscillator itself is misbehaving, failing to oscillate properly, or b) is responding to interference from another source.

To that end, Are the glitches synchronous with the oscillator's 32,768Hz output? If not, what are they synchronous with? Do the glitches stop when you disable the main clock? Do you have a nice bypass cap directly *across* the PIC? (Or, even better, directly bridging load and driver, i.e., the high current paths, whatever they might be.)

Overall, I'd suspect layout until proven otherwise.

Cheers, James Arthur

Reply to
James Arthur

No.

Digital transitions of the adjacent pin (a GPIO pin)

Er, yes, because the GPIO pin stops changing ;-)

As best as I can on a solderless breadboard.

Reply to
DJ Delorie

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