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Yes, of course you have to deal with the details. That's why you get the big bucks. There is plenty of time for the 2GHz counter to ripple through before we read the output with a 100MHz micro. Logic designers have been fighting Sync vs. Async logics for decades, but either one can be made to work.
te:
e , eSure. I first dealt with that particular problem back in 1972, if not at 1GHz.
-- Bill Sloman, Nijmegen
If you end up doing this on an FPGA, consider that a linear feedback shift register with as few taps as possible is going to be a lot faster than a counter -- it'll just be a lot harder to decode the result.
-- www.wescottdesign.com
You can do some interesting things with the SERDES blocks, at 1 GHz.
John
Would a vernier principle be applicable here? Two sligthly offset (lower) frequencies driving two counters being gated by the same signal? Would that achieve anything?
Might want to run the numbers to make sure that what you are asking for is physically possible. A resolution of one microsecond per millisecond at 1 MHz requires a counter rated at 15 digits per second. This is not typically achieved with counters (and to the extent it is, interpolating counters would be used rather than brute- force registers).
Modern T&M gear at this level of play works by downconverting the signal to baseband and measuring the phase slope directly. The phase slope can be integrated within a narrow measurement bandwidth compared to the front end of a counter, which is necessary to keep plain old Johnson noise from turning your LSDs into random digits. Ultimately the phase comparator has to rely on a reference with similar stability, which itself is a research-level problem at 1 fs/s stability. The rabbit hole only goes deeper from there. What exactly are you (or your client) looking to do with this measurement?
-- john, KE5FX
When you say a "resolution of 1 usec..." doesn't that mean, n ± 500 nsec?
That should be almost trivial.
What is it in the spec that calls for 32 bits at 1 GHz?
Thanks, Rich
On the TimeNutsList (febo.com) we once discussed to abuse the xilinx serdes units at 10 GB/sec, but I would never recommend this to a FPGA beginner. You may also google for PICTIC II if the measurement repetition rate is not too high. Or for the operating/service manual of the HP5370A/B time interval counter.
regards, Gerhard
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