250mA voltage clamp

Yes- and then clamp the maximum output regulated voltage at 24V or so when the unregulated gets above 27V or so.

Actually, I don't care about ripple and noise; there's a downstream regulator for the part of the circuit that would care about that. The purpose of this circuit is just to limit the voltage from an unregulated supply so that it does not rise above 24V (give or take a volt). The catch is that I want the input-output differential (when it is not clamping) to be less than 2V, ideally less than 1V.

Several good circuits have been suggested, and I have also been exploring a P-channel MOSFET based circuit that has essentially zero input-output differential when it is not clamping.

Thanks, -walter

Fred suggested using an LDO regulator instead of an LM317, what's wrong with that idea? For example, LTC's LT1085 adjustable 3-term is rated to 3A max and has about 900mV dropout at 250mA. If you're concerned with this IC's 30V max input-output rating (a factor if you short the output with 35V input) you can consider their LT1123, which works with an external transistor to obtain a 250mV dropout.

Bias the GND terminal of this 5V regulator at +19V, to obtain a 24V regulated output and a 49V maximum input-voltage rating. You can make a 19V "zener" using a common TL431 as a shunt reference.

--
 Thanks,
    - Win

Nothing at all wrong with the idea. I just don't happen to have one on hand, and I don't anticipate another parts order till January. So I was hunting around for solutions that used only parts on hand. (I realize that's not a useful spec, since no one else knows what parts I have on hand.)

Here's what I came up with. It uses more parts than some of the suggestions, but I happen to have everything on hand. This circuit appears to work well on the bench; I haven't seen any signs of instability (as long as the .01uF cap is there). The IRFP9240 was chosen only because I've got a tube of them that I'll never get rid of otherwise.

----o---------------o-----+^+--------o------- | | ||| | .-. | === | | | | | IRFP9240 | | |100k PN2907A| | | '-' | .-. | | ___ |< | | | o--|___|-o----| | |1k z | 1k | |\\ '-' A 22V | | | | | | | || | | | | '-||---o-----o | | || | | | .01uF | | | .-. | | | | | | | |10k | | '-' | | PN2222A | | \\| ___ | | |--|___|------------)----------o

That's not a bad approach. You can eliminate both of the 1k resistors, they're not pulling their weight. I'd also reduce the pn2222 base-resistor value. You can add a small pot in series with the zener to trim the output voltage, this adds Vbe * R/470 to the output.

The circuit has three gain elements, the pn2222 with a 100k load, the pn2907 with a 10k load, and the MOSFET with the output load, which usually includes a large capacitor. Each of these elements adds a pole to the feedback loop response, and we know two poles is enough to make an oscillator. Your compensation cap combines two poles, which helps.

To acid-test the loop-stability of the circuit, try a range capacitor values on the output, small to large, and test with each one over the full range of load currents. Inject a small low-frequency square-wave stimulus into the base of the pn2222 through a resistor, and tune the compensation to avoid ringing on the step changes in the output voltage. You will find you can use a smaller feedback capacitor, to speed up the response, if you add a resistor in series with the cap (this adds a zero in the loop response, canceling the cap's pole at a frequency, hopefully in the region where some other element in the circuit is adding its own pole). Let us know how it works out.

--
 Thanks,
    - Win

Thanks!

The 1k in series with the MOSFET gate is there because I was worried about the MOSFET oscillating at RF; there might be an inch or so of wire between the gate (or gate resistor) and the rest of the circuitry, and three or four inches from drain to load. Should I not worry?

The 1k in series with the PN2907 base is there to limit current through the transistors in case the PN2222 turns on hard for some reason. I confess I don't see what could cause that, other than perhaps a momentary short across the MOSFET.

I will do that. It'll be a couple days before I get to it - one of my distributors had a holiday rush and I need to go into assembly-line mode for a little while.

Thanks, -walter

Not on that account, but there is one argument for it, which occurred to me after my posting. The two transistors with the cap feedback act as an integrator stage, which if capacitively loaded might be unstable at high frequencies. Your resistor acts to isolate this stage from the MOSFET's high gate Ciss.

No, that's a good reason. You can keep both resistors. :-)

We'll wait for your next installment.

--
 Thanks,
    - Win

The circuit's three stages bother me, they provide far more loop gain than is required for the job, and they create new problems with loop stabilization. For example, the irfp9240 has 1200pF of gate capacitance, which with the 10k resistor creates a pole at 13kHz. And the MOSFET stage's gain is one giant pole, an integrator whose gain is high but goes through unity at 500Hz to 12.5kHz, depending on the load current, assuming a 22uF load cap. Whew, poles all over the place.

Anyway, I'd feel more comfortable with a simple circuit. Try this one on for size.

. +20 to 50V PMOS 24V regulated . -----+------+-- S D --+------+----+------+---- . | | G | | | | . | 2.2k | | | _|_+ 2.2k . | | | | | --- 0.5W . | +-----' | 18k | 22uF | . 4.7k | | | | | . | c c | gnd gnd . +--- b b ---+ . | e ----+---- e | . \\_|_ | 6.2k . /_\\ 6.2V 1.5k | . | | gnd . gnd gnd

It has a loop gain of 2500 at 100Hz at 0.25A load, which is more than enough, and should be nicely stable if the 22uF electrolytic has more than 55 milli-ohms of esr, which it no doubt will have.

Zeners around 6.2V have very stable characteristics, but you can use other values, if you change the feedback resistors.

--
 Thanks,
    - Win

I wouldn't attempt that with all that unnecessary DC gain. A more stream-lined stand-alone job that is stable with any capacitive loading and reasonable wiring inductance would be more like this: View in a fixed-width font such as Courier.

. . . ___ . .---------------|___|---. . | 1k | . | | . | IRFP9240 | . >---+------o---------+^+------o----o-----------o----->

. | | ||| | | | . | .-. === | .-. | . | | | | === | | | . | | |22k | 100n| | |1.2k | . | '-' | | '-' | . | | | ___ | | | . | '---------o--|___|-' | .---o . | | 220 | | | . | | | | .-. . | | | === | | . +| | | 1u | | |1k . === .---------|-------------' | '-' . 1u | | | | . | | | '---o . | | | | . | 100n | |/ | . o--||--o-------|2N4410 | . | | |> | . | z | | . | A 12V '-------------------------o . | | | . | | .-. . | a | | . | k 1N4001 | |1.2k . | | '-' . | | | . >---o------o-----------------------------------' . | . '------------------------------------------------->

. .

A second transistor can be put to better use as a current limit- foldback left as an exercise for the student: View in a fixed-width font such as Courier.

. . . ___ . .---------------|___|---. . | 1k | . | | . ___ | IRFP9240 | . >---o---|___|-+----o---------+^+------o----o-----------o----->

. | 1.3 | | ||| | | | . | | .-. === | .-. | . o-----. | | | | === | | | . | | | | |22k | 100n| | |1.2k | . | | | '-' | | '-' | . | >| | | | ___ | | | . |2N2907A|-' '---------o--|___|-' | .---o . | /| | 220 | | | . | | | | | .-. . | '------------------|-------. | === | | . +| | | | 1u | | |1k . === .---------|-------------' | '-' . 1u | | | | | . | | | | '---o . | | | | | . | | |/ | | . | -----o-------|2N4410 | | . | | | |> | | . | | z | | | . | 100n| A 12V '-------o-----------------o . | === | | . | | | .-. . | | a | | . | | k 1N4001 | |1.2k . | | | '-' . | | | | . >---o--------+-----o-----------------------------------' . | . '--------------------------------------------------------->

. .

A current limit can be added to this circuit to handle shorts, but such capability means you'll need a much larger MOSFET heatsink. Whereas 35-24V * 250mA created only 2.75 watts power dissipation, under fault-free operation, a short-circuit fault would overheat the MOSFET, damaging the regulator. A 400mA current limit can be added to my circuit with only two components.

. Low-dropout 24V regulator with 400mA current limit . . +20 to 50V PMOS 24V regulated . -----+-- 1.6 -+-- S D -----+------+----+------+---- . | | G | | | | . | b | | | _|_+ 2.2k . +----- e c --+ | | --- 0.5W . | pnp | | | | 22uF | . +-- 2.2k ---+--' | | gnd | . | | | | gnd . 4.7k | | 18k . | c c | . +-------- b b ---+ . | e ----+---- e | . \\_|_ | 6.2k . /_\\ 6.2V 1.5k | . | | gnd . gnd gnd

In the event of a short the heatsink must handle 35*0.4 = 14 watts. If the current limit is converted to a foldback type, which requires two more resistors, this requirement could be reduced to say 4 watts.

--
 Thanks,
    - Win

Posting here is generally a humbling experience for me. Thanks for your patience.

First, re the old circuit: as it turned out, .01uF was not enough to keep it from ringing at all load capacitances and currents. It was worst with around 1uF of capacitance on the load; load resistance didn't seem to make much difference. .033uF was enough to stabilize it for all loads. But your & Fred's criticisms are of course correct.

Moving on to the above circuit: thanks, Win. That seems very simple and straightforward. I built it, and it works nicely and shows no ringing for any load capacitance from .01uF to 100uF.

I am having difficulty repeating your gain calculation, because I don't know how to determine the FET's transconductance, but I will take that up on sci.electronics.basics.

One more question: why is the second NPN's collector fed from the output voltage, rather than from the input voltage?

Thanks again, -walter

That's gratifying. Did you test over a range of load currents?

You're not likely to get a good answer there, unless perhaps someone was looking at AoE figure 3.24, and they dramatically extrapolated the curve for large-area FETs. As it happens, you're operating in the MOSFET's subthreshold region, where its transconductance acts like that of a BJT transistor, only lower by a fixed amount, i.e., g_m = Ic / n Vt, where Vt = 25mV. You know, 25 ohms at 1mA, and proportional to current. I've observed the constant n range from 3 to 10 for different manufacturer's MOSFET types. It appears to have about the same value for different FETs and part runs within a type. There's no hint of the issue, or of its value on most datasheets.

It would work either way. The transistor has a more stable voltage to work from this way, which really doesn't matter... The drawing does look better this way!

--
 Thanks,
    - Win

Just at the min and max; I didn't try intermediate points. I'll give that a try.

I see; I was confused about the subthreshold region. AoE 2ed. section 3.04 gives three equations for Id:

Id = 2k[(Vgs-Vt)Vds - Vds^2/2] (linear region) Id = k(Vgs-Vt)^2 (saturation region) Id = k[exp(Vgs-Vt)] (subthreshold region)

I was thinking that subthreshold described the far left of the Id/Vds graph, but that's wrong, it describes the bottom (low Id, low Vgs, non-zero Vds). Which explains why in the discussion on pp 131-132 you describe a transition from subthreshold to saturation, without any linear in between.

I spent some time last night looking at figure 3.24, but since it shows subthreshold being Id < 1uA I figured that didn't apply here. But you're saying that for this large-area MOSFET, Id in the tens or hundreds of mA still counts as subthreshold, that is, "where the channel is below the threshold for conduction, but some current flows anyway because of a small population of thermally energetic electrons"?

If so, then using your equation at 250mA I'd get gm = 250mA / n 25mV = 10/n = from 1 to 3S. That would give me stage gain of G = gm * Rd = 100 to 300. The gain of the differential stage, biased at 2mA when Vgs is 4.4V, is going to be about Rc / 2re = 90. The resistive divider at the input divides by

3.9. So, 90 * 100 / 3.9 = 2300, I guess I can see how you get a gain of 2500. Is that the right way to do it?

Are there any good references beyond AoE that might have helped me answer this question? (I've just been poking around IRF app notes but didn't see anything relevant.)

Thanks, -walter

Apparently the subthreshold current is modeled with a subthreshold slope , S, which increases, as a constant, with FET channel leakage characteristics. A commonly used fit is: View in a fixed-width font such as Courier.

. . . . . . Vgs-Vt qVds . (--------) -(----) . S/ln(10) kT . I = k x e x [ 1 - e ] . sub . . . The notation is sloppy and the left most k is not Boltzman's . . constant.

I should add, I've measured many different MOSFETs and observed this relationship to be accurate over seven orders of magnitude.

Reference please, Fred.

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 Thanks,
    - Win

Well, five orders anyway. Drain leakage disturbs the fit on the low end. Still, seven orders of fit is obtained if an additional current is accounted for with a parallel leakage resistor, e.g. 5 Giga-ohms for a 1kV FET.

The transition to the saturation region, where Id = k(Vgs - Vth)^2 disturbs the fit on the high end. Looking at some data I've taken, this starts at currents above 0.1% to 0.5% of the FET's maximum operating current.

A 0.1% transition threshold is lower than I'd remembered, and may put Walter's 250mA operation of an IRFP9240 well into this region, reducing its g_m from my estimates. More detail in my answer to Walter in this thread I plan for later today.

The first term isn't the exactly form I'd use, but it's not in disagreement with my g_m formula. The second term dealing with drain voltage, appears practically irrelevant over most of the subthreshold region, where the drain current is set by Vgs, and isn't much affected by Vds, for Vds > 200mV, etc.

--
 Thanks,
    - Win

Thanks, I find that S/ln(10) term less helpful than my "n V_T" term, but either form has a huge user-adjusted fudge factor.

--
 Thanks,
    - Win

The best I can do is two levels of indirection removed from the original. My original is FPGA-Based System Design by Wolf who references Low-Power CMOS VLSI Circuit Design by Roy and Prasad, both are books.