Ceramic capacitor polarity trick

I don't quite get your question. If the app won't allow electrolytics, and you have a MLCC, what's the problem?

More details would help too. What capacity, what voltage, what allowable leakage current?

Yes... this is perfectly feasible. However you have to realise that there are people who don't know about this stuff who will suggest that by making one of the terminals more positive or possibly negative (depending on the polarisation they think you want) then your capacitor will be polarised. They think they are clever but we know they are wrong.

There are two effects that you are looking at here, one is for shielding and the other is for the piezo-electric effect.

As you know your capacitor is a Multi-Layer device and, in the case of shielding, we are interested in the way that the 'Layers' have been layed down by the manufacturer and how they are connected to the terminations.

Obviously, for puposes of shielding, it is very important that the first layer and the termination it is connected to must be at the lowest or ground potential when referenced to possible sources of interferance.

So, if your capacitor is likely to receive interferance from the board it should be placed with the first layer close to the board and the associated termination connected to circuit ground.

Of course, if you are looking to minimise external interference then the first layer should be uppermost and the associated termination connected to circuit ground.

Getting this wrong is a common mistake and unavoidable when buying multi-layer devices from a manufacturer who does not screen and package their product in a manner that allows your pick and place machine to perform its function correctly according to your specific design requirements.

If you require to apply a DC bias to your Multi-Layer capacitors then, like others who really know about this sort of problem, you are looking to pre-stress the devices to drive the resonant frequency where piezo-electric effects become apparent above common and future sampling rates to avoid the problems of aliasing.

Once again, as is typical with board applied products such as femptodamp(TM), it is important to verify that your Multi-Layer capacitors are correctly oriented on the board so that the applied DC bias causes flexure of the device towards the board applied layer to give proper contact along with the required levels of stiffening and damping.

Your Multi-Layer capacitor manufacturer should be able to help you with the information you require about the relevant layers, termination process and bias polarity required for correct flexure of the materials they use.

DNA

In message , dated Fri, 4 Aug

Why not just make sure the signal flow is in the direction that the value marking reads?

Here we go, another bloody presumed expert.

Do surface mount MLCC capacitors have markings on them.... ay? I mean do they?

NO, so you have to get them from the right place and then you will get TOP and an arrow marked on them.

It's not as if life was any better when capacitors looked like liquorice allsorts and I'm damned sure you couldn't claim anything about which way to stick the buggers in since the stripes were horizontal!!!!!!

DNA

In message , dated Fri, 4 Aug

Well, of course; you could put those in either way round.

Sheesh.

So how did you know whether they were wound clockwise or anti-clockwise?

DNA

In message , dated Fri, 4 Aug 2006, Genome writes

They were all wound clockwise if looked at from the right end.

Won't work either. A Schottky diode has a very low forward voltage drop. An electrolytic cap doesn't have much reverse leakage at that sort of voltage.

Best regards, Spehro Pefhany

Yes, sometimes you need to add a small resistor (1 ohm or something like that) in series with a ceramic cap for hysteretic converters. Also for required stability with some LDO regulators.

Best regards, Spehro Pefhany

A non-polarised capacitor will work anywhere a polarised one is used correctly.

The only reasons polarised capacitorsd are ever used is because they are cheaper and smaller than non polarised ones.

They can also explode but that's generally when they are used incorrectly.

Bye. Jasen

I wouldn't suggest it's good circuit design, but I don't really think this is true. My understanding is that electrolytic capacitors will look more or less like a short circuit when reverse polarity is applied to them -- hence the common suggestion of using two electrolytics "back to back" to build a non-polarized cap from two polarized ones. As such, I wouldn't be surprised if someone's circuit somewhere relies on this behavior to eliminate, e.g., a Schottky diode in parallel with an unpolarized cap.

---Joel

I don't think so. There's more leakage, and damage if the reverse polarity is applied for long enough and high enough, but it's nothing like a short circuit. A quick check with an ohmmeter, or a look at the schematic of some cheapo audio gear (where polarized elcaps are often used just like nonpolarized ones to pass low-voltage AC signals with minimal DC bias, eg the output of an opamp with a bit of offset voltage), is enough to confirm that.

In message , dated Fri, 4 Aug 2006, Joel Kolstad writes

I don't believe any elco maker would regard that as anything other than serious abuse.

Elcos used in audio coupling with zero bias perform far, far better than most ppl believe actually. Hence their use in professional audio in this configuration.

Graham

I had a switch-mode regulator circuit where I had to use an electrolytic - the chip capacitor I used had too low an impedance and made it unstable. It was a "hysteretic" mode buck regulator IIRC.

In message , dated Sat, 5 Aug

It's more 'designable' to use a chip cap with a series resistor. You can't rely on the ESR of elcos.

I'd suggest that that'd be using the capacitor incorrectly :)

Bye. Jasen

Spehro Pefhany wrote in news: snipped-for-privacy@4ax.com:

Nice tip. Thankyou.

It's not possible for a hysteretic to become unstable. The main issues there are bounding frequency of operation across all possible combinations of input voltage and output loading, and achieving low output ripple at high ratios of output to reference. The first is overcome by using a topology of fixed ON time inversely proportional to input voltage magnitude with some non-linear foldback to handle discontinuous mode, and the second by various little RC feedback networks containing zeroes that pass the ac-component of ripple unattenuated.