Output Z of CMOS Current Mirror ??

That's a lot of capacitance in the CMOS world... 30fF ;-)

...Jim Thompson

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|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
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I love to cook with wine.      Sometimes I even put it in the food.

Doesn't 1G-ohm at 5KHz imply no more than .03pf of parallel capacitance?

--
John Popelish

I've done 32khz xtal oscillators than ran

Thought you guys had it cracked long ago with the 100's of Mohms of cascoded Wilson mirrors. Looks like you'll be marking out some virgin turf :). regards john

Why?

Maybe there another way to do achieve the same function.

Anyway, what am I missing? I just checked a standard 3 stack cascoded current mirror, using my generic Bsim models, L=1u, w=1u, I=1ua, and got

345 Gohm < 100Hz falling to 29 Gohm at 10K. At 10ua it was flat to 10Khz at 11 Gohms.

So, what current are you trying to do this at?

Kevin Aylward snipped-for-privacy@anasoft.co.uk

SuperSpice, a very affordable Mixed-Mode Windows Simulator with Schematic Capture, Waveform Display, FFT's and Filter Design.

Take a look at these active-feedback cascoded mirrors - they manage about 16fF output capacitance:

Electronics Letters , Volume: 33 , Issue: 12 , 5 June 1997 pages 1042 - 1043.

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Rick

In sci.electronics.cad Jim Thompson wrote: : Anyone have experience at creating a CMOS current mirror with really : high output Z?

: I'm trying attain about 1G-ohm, at 100Hz to 5KHz.

: I can use cascodes and feedback loops.

: Just thought I'd ask before I plunge in and shoot myself in the foot : ;-)

1GOhm at 5kHz is about 30 fF. Good luck in getting down the capacities...

Bye

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Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

I once managed to screw up a pwm to +/-10V output circuit, with a mere

60fF of stray capacitance. I got 100mV spikes in my output, synchronous with the pwm. Aha I sez to myself, a capacitive coupling issue. So I looked at the pcb, and found the pwm signal ran near the opamp inverting input - 8mil away, for 9mm or so. I did a quick calc, and found about 60fF. Rubbish I sez to myself, thats tiny, it cant be causing this. So I went and measured PWM dV/dt and output spike amplitude. I ran backwards thru the opamp to work out what current caused the V, and guess what - 60fF*dV/dt = just the right amount of current. A little surgery with a small drill and a bit of wire-wrap wire, and voila - no problem. I moved the trace on the pcb, and the production version worked a treat.

Cheers Terry

Would routing a ground trace between them have fixed it?

Most certainly, although in this case I looked at the layout and changed it quite significantly - it had been done by one of our techs (he did most of the pcb layout) and he was more concerned with joining the dots than thinking about the circuit he was building. The layout as implemented was terrible, with really poor part placement leading to nasty interconnects and many vias. A simple re-arrangement of top-layer components made the design flow nicely, and removed a whole bunch of vias and inner-layer traces. That was when I first started to approach pcb layout as a circuit design problem. When I lay out a pcb nowadays I typically spend 80-90% of my time placing components, and do the copper last. Its perhaps a bit slower, but the circuits tend to work a lot better.

Cheers Terry