More or less, yes, but the curves still all use the same basic equation. Vt and beta (transconducance parameter) are essentially independent, so you can have any K.W/L with any Vp.
Kevin Aylward snipped-for-privacy@anasoft.co.uk
Hi all,
Say a datasheet lists values of
Idss= 20mA - 60mA Vp= 2V - 6V
(pulling plausible figures out of the air)
Typical values rarely seem to be listed for FETs, so I assume there's a fairly even distribution of real-world manufacturing variations between the two extremes.
Now the question is, one would expect the FET with the Idss of 20mA to have a Vp of 2V in the above example, and one with an Idss of 60mA to have a Vp of 6V, thereby preserving the characteristic shape of the curve across the whole range of possible values. But is it possible to get the occasional rogue real-world FET that has a Vp of 2V and an Idss of 60mA or one with a Vp of 6V that gives an Idss of 20mA, thereby with totally different characteristic curves?
Thanks,
p.
-- "What is now proved was once only imagin\'d." - William Blake, 1793.
Aparantly not.
Did you remove EXTRACT. The other one is kevin.aylward with the obvious addition.
Kevin Aylward snipped-for-privacy@anasoft.co.uk
Did you get my e-mail, Kev?
-- "What is now proved was once only imagin\'d." - William Blake, 1793.
I assume you own the domain in question? Ergo, any old string before the @ should get through. Ah! I see. I take that back. I'll resend it now with the appropriate bit removed.
-- "What is now proved was once only imagin\'d." - William Blake, 1793.
No. I set it up to bounce back if not exactly correct. Two much spam otherwise.
Ah! I see. I take that back. I'll resend it
And working on the new bug you discovered!
Kevin Aylward snipped-for-privacy@anasoft.co.uk
[snip]
The correspondance is nearly but not quite.
They will have 100% measured Idss to select out chips suitable for that particular part number. So you can believe the 24-60mA Idss for your J310's. But the -2 to -6.5V Vgs(off) min/max values are not measured, they are taken from the nominal values for the source chip, with the window widened-out (for tolerancing and the problems of leakage current when packaged).
The old Siliconix data manuals would give data for both the device and source chip. The original U310/E310/J310 devices were selected from their wafer/chip known as NZT. (But see note at end.)
One of the graphs on the NZT data sheet is a plot of Idss versus Gate-Source Cutoff Voltage. It shows that a 24mA chip would have a typical Vgs(off) of about -2.7V and a 60mA chip about -4.5V.
Those are the two Vgs(off) numbers we would use when doing the two Id= Idss(1 - etc ) curves to find the nominal Id biassing point for an E310.
Note that the Vgs sums only work when Vds is relatively high, normally taken as at least 2x the maximum Vgs(off).
Note: The NZT data was taken from a 1979 Siliconix book, but I see that by 1986 they were taking J310's from their NZA wafer/chip. The 24-60mA Vgs(off) voltages have changed slightly for the NZA, to -1.9V and -4V respectively. This is probably more representative of a recent J310.
-- Tony Williams.
Take a look at PHEMTs. They mostly have very repeatable transfer curves. The Fujitsu (just renamed to Eudyna, whatever that means) FSU-series are amazing; looking at pulsed transfer curves, you literally can't tell two fets apart. Transconductance is like 0.1 and capacitances are very low; much better for RF than jfets.
The PHEMTs have lots of gate leakage, 1/f noise, and a very strange low-frequency dispersion mechanism that makes them unsuited to many low-current or low-frequency applications.
John
My favorite Taiwanese company name is "Mean Well Electronics."
John
I read in sci.electronics.design that John Larkin wrote (in ) about 'FET transfer function - best and worst cases', on Sat,
11 Sep 2004:Greek, 'good force'.
-- Regards, John Woodgate, OOO - Own Opinions Only. The good news is that nothing is compulsory. The bad news is that everything is prohibited. http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk
Muslims reckon that if you wipe your arse with the right hand, it's unlucky.
-- "What is now proved was once only imagin\'d." - William Blake, 1793.
Like a number of (apparently) religious strictures, it has a basis of practicality. In any country with little water it is not always practical to wash properly. So you wipe your arse with your left hand, and make damned sure you only use your right hand to eat with.
Get things mixed up, and you are almost guaranteed to be 'unlucky'.
-- Tony Williams.
Mine is "Sure Fire Electrical".
Best regards, Spehro Pefhany
-- "it\'s the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com
Which is why removing the right hand surgically is a ticket to being shunned for life. Nobody wants some dude fishing around in the communal food bowl with his wiping hand.
Best regards, Spehro Pefhany
-- "it\'s the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com
Blimey! Never thought of that.......
-- Tony Williams.
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