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XPower help.

Hi All,

I am using XPower and I encounter the following warnings: WARNING:Power:762 - Only 61% of the design signals have been set. WARNING:Power:763 - Only 49% of the design signals toggle. INFO:Power:556 - Estimate is inaccurate based on analysis of the design, user input and characterization data.

I am using the post-place-and-route simulation model and the activities of all nodes are set by ModelSim using a vcd file simulating up to 10000 cycles.

1) Specifically, how does it determine that the estimate is inaccurate?

2) Are register-rich designs tend to be like that i.e. because activities at varoius nodes has not been set properly?

3) WHAT CAN I DO?

The detailed report is below:

---------------------------------------------------------------- Release 6.3.01i - XPower SoftwareVersion:G.36 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Design: stream Preferences: stream.pcf VCD File: stream.vcd Part: 2v1000ff896-6 Data version: ADVANCED,v1.01,07-31-02

Power summary: I(mA) P(mW)

---------------------------------------------------------------- Total estimated power consumption: 567 --- Vccint 1.50V: 103 154 Vccaux 3.30V: 100 330 Vcco33 3.30V: 25 83 --- Clocks: 1 1 IOs: 0 18 Inputs: 0 0 Logic: 1 1 Outputs: Vcco33 19 62 Signals: 1 1 --- Quiescent Vccint 1.50V: 100 150 Quiescent Vccaux 3.30V: 100 330 Quiescent Vcco33 3.30V: 1 3 Startup Vccint 1.5V: 250 Startup Vccaux 3.3V: 100 Startup Vcco33 3.3V: 50 --- Package power limits, ambient 25C: 5085 250 LFM: 7317 500 LFM: 8955 750 LFM: 10169

Thermal summary:

---------------------------------------------------------------- Estimated junction temperature: 32C 250 LFM 30C 500 LFM 29C 750 LFM 28C Ambient temp: 25C Case temp: 31C Theta J-A: 12C/W --- Max ambient at junction max of 85C: 78C 250 LFM 80C 500 LFM 81C 750 LFM 82C

Decoupling Network Summary: Cap Range (uF) #

---------------------------------------------------------------- Capacitor Recommendations: Total for Vccint : 44 470.0 - 1000.0 : 1 4.70 - 10.00 : 2 0.470 - 2.200 : 5 0.0470 - 0.2200 : 8 0.0100 - 0.0470 : 14 0.0010 - 0.0047 : 14 --- Total for Vccaux : 8 470.0 - 1000.0 : 1 0.0470 - 0.2200 : 1 0.0100 - 0.0470 : 2 0.0010 - 0.0047 : 4 --- Total for Vcco33 : 11 470.0 - 1000.0 : 1 0.470 - 2.200 : 1 0.0470 - 0.2200 : 2 0.0100 - 0.0470 : 3 0.0010 - 0.0047 : 4 ----------------------------- I/O Bank Details:

Bank 0 (3.3V) : 470.0 - 1000.0 : 1 0.470 - 2.200 : 1 0.0470 - 0.2200 : 2 0.0100 - 0.0470 : 3 0.0010 - 0.0047 : 4 Total : 11 ---

---------------------------------------------------------------- For further information on Bypass/Decoupling Capacitors see application note 623

WARNING:Power:762 - Only 61% of the design signals have been set. WARNING:Power:763 - Only 49% of the design signals toggle. INFO:Power:556 - Estimate is inaccurate based on analysis of the design, user input and characterization data.

Power details:

------------------------------------------------------------------------------- Outputs:1 Loads Loading(fF) C(pF) F(MHz) I(mA) P(mW)

------------------------------------------------------------------------------- Vcco33 mpc_d-E0 35000 13 5.1

0.8 2.7 mpc_d-E0 35000 13 5.1 0.8 2.7 mpc_d-E0 35000 13 5.1 0.8 2.7 mpc_d-E0 35000 13 5.1 0.8 2.7 mpc_d-E0 35000 13 5.1 0.8 2.7 mpc_d-E0 35000 13 5.1 0.8 2.7 mpc_d-E0 35000 13 5.1 0.8 2.7 mpc_d-E0 35000 13 5.1 0.8 2.7 mpc_d-E0 35000 13 5.0 0.8 2.6 mpc_d-E0 35000 13 4.9 0.8 2.6

------------------------------------------------------------------------------- Logic: Loads Loading(fF) C(pF) F(MHz) I(mA) P(mW)

------------------------------------------------------------------------------- CompRegD345-E1 1 10.0

0.0 0.0 CompRegB378-U1/SP.WSGEN 0 10.0 0.0 0.0 CompRegB378.WSGEN 0 10.0 0.0 0.0 CompRegB381-U1/SP.WSGEN 0 10.0 0.0 0.0 CompRegB381.WSGEN 0 10.0 0.0 0.0 CompRegB384-U1/SP.WSGEN 0 10.0 0.0 0.0 CompRegB384.WSGEN 0 10.0 0.0 0.0 CompRegB387-U1/SP.WSGEN 0 10.0 0.0 0.0 CompRegB387.WSGEN 0 10.0 0.0 0.0 CompRegB583-U1/SP.WSGEN 0 10.0 0.0 0.0

------------------------------------------------------------------------------- Signals: Loads Loading(fF) C(pF) F(MHz) I(mA) P(mW)

------------------------------------------------------------------------------- __ibuf_mpc_a 33 19 2.8

0.1 0.1 __ibuf_mpc_a 33 19 2.8 0.1 0.1 __ibuf_mpc_a 33 19 2.5 0.1 0.1 __ibuf_mpc_a 33 17 2.2 0.1 ~0.0 __ibuf_mpc_oe 36 9 3.2 0.0 ~0.0 CompRegC216 78 23 0.9 0.0 ~0.0 internal_mpc_d 1 3 5.1 0.0 ~0.0 internal_mpc_d 1 2 5.1 0.0 ~0.0 internal_mpc_d 1 2 4.9 0.0 ~0.0 internal_mpc_d 1 2 4.8 0.0 ~0.0

------------------------------------------------------------------------------- Clocks:1 Loads Loading(fF) C(pF) F(MHz) I(mA) P(mW)

------------------------------------------------------------------------------- stream/clk/IBUFG Logic: stream/clk/BUFG 6 10.0

0.1 0.1 Nets: stream/clk 94 38 10.0 0.6 0.9 stream/clk/IBUFG 1 0 10.0 0.0 ~0.0

------------------------------------------------------------------------------- Inputs: Loads Loading(fF) C(pF) F(MHz) I(mA) P(mW)

------------------------------------------------------------------------------- stream/clk/IBUFG 3 10.0

0.1 0.1 __ibuf_mpc_oe 3 3.2 0.0 0.0 __ibuf_mpc_a 3 3.0 0.0 0.0 __ibuf_mpc_a 3 2.8 0.0 0.0 __ibuf_mpc_a 3 2.8 0.0 0.0 __ibuf_mpc_a 3 2.8 0.0 0.0 __ibuf_mpc_we 3 2.8 0.0 0.0 __ibuf_mpc_a 3 2.7 0.0 0.0 __ibuf_mpc_a 3 2.6 0.0 0.0 __ibuf_mpc_a 3 2.5 0.0 0.0

------------------------------------------------------------------------------- IOs:1 Loads Loading(fF) C(pF) F(MHz) I(mA) P(mW)

------------------------------------------------------------------------------- Vcco33 __ibuf_mpc_d 3 5.3

0.0 0.0 mpc_d-E0 35000 13 5.2 0.8 2.7 __ibuf_mpc_d 3 4.9 0.0 0.0 mpc_d-E0 35000 13 5.2 0.8 2.7 mpc_d-E0 35000 13 4.9 0.8 2.6 __ibuf_mpc_d 3 5.5 0.0 0.0 __ibuf_mpc_d 3 5.8 0.0 0.0 mpc_d-E0 35000 13 4.8 0.8 2.5 __ibuf_mpc_d 3 5.2 0.0 0.0 mpc_d-E0 35000 13 4.8 0.8 2.5

-------------------------------------------------------------------------------

Power improvement guide:

------------------------------------------------------------------------------- 3 of 101 registers use an enable signal

------------------------------------------------------------------------------- Signal Power when Power when Power savings asserted(mW) disabled(mW) at

50%(mW)

------------------------------------------------------------------------------- AddrInCount355/Start-E0 567.1 567.1 0.0

For further suggestions on power improvements see application note no.

421

Analysis completed: Sat Oct 02 16:28:00 2004

----------------------------------------------------------------

Reply to
Ted
Loading thread data ...

Ted,

It is trying to tell you that your simulation test bench doesn't cause much to happen.

The estimate is only as good as the test bench.

If all those nodes don't ever switch, then you can probably simplify your design!

The number of cycles is no measure of coverage. If I hold a register in reset, and clock it a million times, I will not see much power.

So, without a test bench that exercises all of the registers, with the worst case transitions, the estimate isn't very good.

But only you can tell what the register values should be, the tool can't just guess.

Some people use a LFSR to generate pseudo random data as a stimulus. Might, or might not be appropriate in your case.

Aust> Hi All,

Reply to
austin

Hi Austin,

Thanks for your reply. Makes a lot of sense.

I can understand the part on 49% of signals not toggling relating to the situation you are talking about.

How about the setting of signals (61%).

1) Does this mean that the information is not transferred by the vcd file or

2) No activity is detected so it is not reflected (In which case there is no difference from not toggling)

If it is 1), I guess it is the fault of settings in ModelSim, how then can I address the problem? The format of my modelsim script is as follows:

add wave sim://* vcd file .vcd vcd on vcd add /* force run

Thanks Ed

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Reply to
Ted

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