Xpower - Clock Power

Before using xpower for my design, I decide to check for a simple design of fibonacci series. I am facing following issues:

I am running xpower with vcd generated with post par simulation and during parsing I encounter the following warnings:

WARNING:Power:91 - Can't change frequency of net CLK_BUFGP/IBUFG to

741.84Mhz. WARNING:Power:91 - Can't change frequency of net CLK_BUFGP to 741.84Mhz. WARNING:Power:91 - Can't change frequency of net CLK_BUFGP/IBUFG to 741.84Mhz. WARNING:Power:91 - Can't change frequency of net CLK_BUFGP to 741.84Mhz. ...

The frequency for signals in data view shows some values inthe range of 2-9% in all cases except CLK_BUFGP/IBUFGP and CLK_BUFGP.. Any attempts to change this value results in power:91 warnings as above.

The confidence level shows Accurate. I am confused as the report shows zero power for clock/ logic nets and still the confidence level is accurate. The report summary is :

Total estimated power consumption: 439 Peak Power consumption: 1081711 --- Vccint 1.50V: 65 98 Vccaux 3.30V: 100 330 Vcco33 3.30V: 3 11 --- Clocks: 0 0 Inputs: 0 0 Logic: 0 0 Outputs: Vcco33 2 8 Signals: 0 0 --- Quiescent Vccint 1.50V: 65 98 Quiescent Vccaux 3.30V: 100 330 Quiescent Vcco33 3.30V: 1 3

Whats going wrong here? Anybody encountered similar problems? Feedback/ help from Xilinx folks please.

-- Mukesh

Reply to
Mukesh
Loading thread data ...

This does indeed look similar to another problem which we've been working on. We have a fix for that problem (the one we've been working on) and the fix will be available in the next service pack - 6.3.01i - which should be available to you next week. However, you might be experiencing a diferent symptiom. One option would be for you to zip up the NCD & VCD file and send them to us ? Or are they huge ? The other option is for you to try the service pack next week. Note - in order for you to use

6.3.01i you'll need to have the underlying 6.3i. (From your other e-mail to the newsgroup it appears you are using 6.2.03i.)

Brendan

Reply to
Brendan Cullen

Hi Brendon,

Thanks Brendon for the response. Yes, I am using 6.2.03i of xpower. Can I get web updates? Also, do we need to get update for xpower alone or we have to get for complete ISE. I also saw on xilinx web site that ISE 6.3i is released too on

9/13. Pls clarify what all i need to upgrade if I have ISE 6.2 and xpower 6.2.03i

-- Mukesh

Reply to
Mukesh Chugh

You can. Our service packs are available on the web.

Complete ISE.

There are two steps :

- Firstly you need to upgrade to 6.3i. That is not a web release. That is a CD-based release.

- Then you need to download (from the web) 6.3.01i

Regards,

Brendan

Reply to
Brendan Cullen

HI

I would like to confirm that my flow is correct. I am checking the Power consumption of some final state machines. The begining is the kiss file with the state machine, next I am encoding and synthetizing it with SIS (berkeley university product) tool. After that I am receiving the blif file. Using our own tool I am converting this blif to edif which is full yrecognizable by the ISE tool. I am making mapping of this edif, generating testbench simulating it with modelsim and when I hav .vcd file from model sim I am using the xpower tool. The results for this files are mostly resonable or inaccurate.

When I checked the same flow with our own tool most of the results is accurate and only some of them is inaccurate.

Do you when can be the problem?? If my explanation is not full just let me know, then I will highlight the points which are not clear.

thank you in advance

regrads

Dom> Hi Mukesh,

Reply to
Dominik Gawlowski

You will get a more accurate result if you run PAR on the design after MAP. Let me know if things improve when you do that.

Regards,

Brendan

Reply to
Brendan Cullen

Hi thank you for your response

I have a following flow in ISE software:

ngdbuild -intstyle ise -dd _ngo -i -p xc2v1000-fg256-4 $EDF data.ngd

netgen -intstyle ise -tb -rpw 100 -tpw 0 -ar Structure -ti UUT -xon true

-w -ofmt vhdl -sim data.ngd data_translate.vhd

map -intstyle ise -p xc2v1000-fg256-4 -cm area -pr b -u -k 4 -c 100 -tx off -o data_map.ncd data.ngd data.pcf

par -w -intstyle ise -ol std -t 1 data_map.ncd data.ncd data.pcf

trce -intstyle ise -e 3 -l 3 -xml data data.ncd -o data.twr data.pcf

netgen -intstyle ise -s 4 -pcf data.pcf -ngm data_map.ngm -tb -rpw 100

-tpw 0 -ar Structure -ti UUT -xon true -w -ofmt vhdl -sim data.ncd data_timesim.vhd

$EDF is a variable which is calling my edif file which is created from kiss.

As you can see, the mapping is made before PAR, And the strangest think is that if I am using our tool to make blif and our tool to make edif, almost all results are accurate or reasonable.

When I am using SIS (berkeley)tool to make blif and our tool to make edif, then most of the results are inaccurate or reasonable, which means that when I am trying to take values of the power I have always the same result.

The second question I have is about the 1-hot binary gray and jedi encoding. I have tried to use xst tool to encode the FSM converted from Kiss format to verilog, but I was unsuccessful. Do you have any idea, how the flow should looks like??

Thank you in advance

regards

Dom> Hi Dominik,

Reply to
Dominik Gawlowski

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.