Before using xpower for my design, I decide to check for a simple design of fibonacci series. I am facing following issues:
I am running xpower with vcd generated with post par simulation and during parsing I encounter the following warnings:
WARNING:Power:91 - Can't change frequency of net CLK_BUFGP/IBUFG to
741.84Mhz. WARNING:Power:91 - Can't change frequency of net CLK_BUFGP to 741.84Mhz. WARNING:Power:91 - Can't change frequency of net CLK_BUFGP/IBUFG to 741.84Mhz. WARNING:Power:91 - Can't change frequency of net CLK_BUFGP to 741.84Mhz. ...The frequency for signals in data view shows some values inthe range of 2-9% in all cases except CLK_BUFGP/IBUFGP and CLK_BUFGP.. Any attempts to change this value results in power:91 warnings as above.
The confidence level shows Accurate. I am confused as the report shows zero power for clock/ logic nets and still the confidence level is accurate. The report summary is :
Total estimated power consumption: 439 Peak Power consumption: 1081711 --- Vccint 1.50V: 65 98 Vccaux 3.30V: 100 330 Vcco33 3.30V: 3 11 --- Clocks: 0 0 Inputs: 0 0 Logic: 0 0 Outputs: Vcco33 2 8 Signals: 0 0 --- Quiescent Vccint 1.50V: 65 98 Quiescent Vccaux 3.30V: 100 330 Quiescent Vcco33 3.30V: 1 3
Whats going wrong here? Anybody encountered similar problems? Feedback/ help from Xilinx folks please.
-- Mukesh