Xilinx/Altera gate equivalence

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Are there any rules of thumb to figure out the equivalent number of
logic resources
needed to implement the same design on Stratix IV vs., say,
Virtex-4/5?
I am thinking of random logic, i.e. a CLB vs. LAB conversion factor...

Thanks!

Re: Xilinx/Altera gate equivalence
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Quartus will give the exact utilization
and pick a device for you, if you have source code.

        -- Mike Treseler

Re: Xilinx/Altera gate equivalence
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I don't, and that's why I am asking... I have a Virtex-4 design and
I'd like to find what Stratix IV
part it will fit in.


dudesinmexico

Re: Xilinx/Altera gate equivalence
dudes,

If you contact your Xilinx FAE I am sure they would be happy to help you.

If this is an academic study, then I suggest you will have to get
somewhere from one to five hundred designs, and then target them to each
architecture, and then examine the results, and try to draw some
conclusions.

Of course, whatever designs you choose will be challenged as being the
'wrong' ones, or ones that are 'obviously biased.'

Personally, I believe market forces are at work so that the cost of
doing whatever you want to do is roughly equal between the two choices.

Then it becomes a question of component availability, lowest power, or
fastest speed, or best IP libraries, or best support.

Or, a question of all of the above.

Austin

Re: Xilinx/Altera gate equivalence
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So these days Xilinx FAEs help their customers to port their designs
to Altera?
Sorry Austin, I could not resist.. ;)
Anyway, this is not an academic exercise. Porting a very complex
Virtex4 design
to Stratix is not something that one can do in a few days, so I was
looking
for ballpark estimates about the equivalence between Xilinx and Altera
"gates".


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Re: Xilinx/Altera gate equivalence

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Have you looked at the Stratix data sheet?  Did you find anything
close to a CLB/FF pair?  If so, assume they are 1:1.

Then count the special things you use: BRAMs, clock buffers, multipliers
and whatevber.  Then see if Altera has something similar.

--
These are my opinions, not necessarily my employer's.  I hate spam.


Re: Xilinx/Altera gate equivalence
On 17 jul, 05:00, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal
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Hi,

I have searched before about the comparison Logic Elements and Logic
Cells. Most of the result say LE 3D% LC, but once (@ Altera website) I
found that LE 3D% 1.125*LC

Bye
Bert

Re: Xilinx/Altera gate equivalence
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This highly depends on the actual design, there are some minor
differences between LEs and LCs that might or might not have an
advantage for certain designs. Nevertheless estimating 1:1 is a fairly
good choice in my opinion. At least as long as you do not want to go
without any reserve of LEs/LCs.

Regards,

Lorenz

Re: Xilinx/Altera gate equivalence
There is a comparision done by Altera between Stratix III an Virtex-5

http://www.altera.com/products/devices/stratix-fpgas/stratix-iii/overview/architecture/performance/st3-opencores.html

Maybe I missed it, maybe it is not mentioned, but I cannot find the
HDL-compiler used and its settings thus the results might vary and You
should not fully rely on a vendor's result (especially if the vendor
wins against his competitor in the result).

But there You will find a technical description on how to perform such a
test-case. This possibly might help.

Regards,

Lorenz

Re: Xilinx/Altera gate equivalence

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I don't think so. I guess the best estimate is to determine the amount
of flipflops in use in both normal flipflops and LUT ram. You'll need
an Altera device with at least that amount of flipflops. Next thing
you'll need to compare blockrams, multipliers, etc. But the latter is
relatively easy.

--
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)

Re: Xilinx/Altera gate equivalence
On Wed, 16 Jul 2008 17:20:10 -0700 (PDT), dudesinmexico

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maybe he means "help" as in "set you right about such a silly idea" :-)
or, being optimistic, ... maybe he means, provide a discounted price to
keep you with Brand X?

- Brian


Re: Xilinx/Altera gate equivalence

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I agree with Austin.
Pricing is roughly equivalent because of competition.
There is no better estimate without a redesign.
Porting a design without source code sounds painful to me.
I would leave it alone if cost is the only reason for change.

         -- Mike Treseler

Re: Xilinx/Altera gate equivalence

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1) Get an evaluation license for Precision/Synplicity
2) Download a number of large free design from the web
3) Synthesize for Virtex4/Stratix4
4) P&R the designs, compare Area/Delay

IMHO there is very little point in comparing large FPGA's from an
architectural point of view without including the Synthesis/P&R factor.

Hans
www.ht-lab.com






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