simulating xilinx clkdll

Hi,

I have some troubles simulating a clkdll primitive with modelsim.

I included a clkdll mapping in my VHDL project to do a clk2x and clk4x. After synthesis, all is working fine about frequency value (I have a 40

- 80 - 160 MHz).

But now I have to simulate all of this with the main design. BUT how can I simulate CLKDLL without body description of the unisim library.

For now, I just did a new VHDL architecture for my CLKDLL. But are there a better solution for simulation!

Best Regards, Laurent Gauch

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