I wonder if anyone (Xilinx?) has actual information on Spartan3e fabric speeds?
I have done some actual measurements and as far of the results the LUT propagation delay seems to be about 10% bigger than in S3?
This info seems to be obmitted in Spartan3e datasheets. Oh well, it looks like will have to rely on our measurements when the manufacturer does not publish the timing info.
I was hoping to see a little speed improvment so seeing 10% decrease was a small surprise. Well I have not tested all the S3e I have yet maybe other parts are actually faster than the one used for LUT speed testing.
"Austin Lesea" schrieb im Newsbeitrag news:dqj55h$ snipped-for-privacy@xco-news.xilinx.com...
Hi Austin,
Ok, thats fair enough - I have 3 different S3e chips but I have not measured all of them, the first one I did measure did show 10% LUT delay increase compared to S3 slowest speed grade. Sure the 10% can be process variations and I need to measure more devices in order to see the actual difference if there is any.
I was hoping to see speed increase, and as it wasnt there so I asked if there known the speed timing differences.
"Austin Lesea" schrieb im Newsbeitrag news:dqjfba$ snipped-for-privacy@xco-news.xilinx.com...
hmmm.. I have following chips for testing:
100e
250e
500e
are all of them from the same wafer ??
ROTFL that would be nice design, make one wafer and cut smaller pieces for smaller FPGAs
hm that may not be impossible actually... just make whole wafer full of the fabric interlaced with IOB then cut out different rectangles and get different sized FPGAs
No, they are not. But they may all be from the same weeks, running the same process, on the same equipment, and thus very similar.
There are things that sound crazy, but then you end up thinking how to do them. This is one area where we are still looking for a way to make all our parts at once, and just slice off the ones you need.
So far, there is no way to do this, but we are still thinking about it!
Antti, each of these devices comes from its own wafer. We do not mix different device sizes on the same wafer. Regarding speed: Spartan3E never claimed to be faster than Spartan3. Both use the same technology. For S3E, low cost was the primary objective. The S3E data sheet says: ...to meet the need of cost-sensitive consumer applications... ...more logic per I/O... ...new features improve system performance... ...more functionality and bandwidth per dollar...
That's as close as any data sheet will ever come to stating: "This is not meant to be a speed demon". Peter Alfke
"Peter Alfke" schrieb im Newsbeitrag news: snipped-for-privacy@o13g2000cwo.googlegroups.com...
Hi Peter,
no problems even there are missing 10% speed (maybe there isnt I have not finsihed the testing)
I just was silently hoping to see higher in-fabric clock speeds
I was trying to figure out what are the max clocks that the S3e can work so I tried it out, so for time being the fastest clock am able to use in S3e is about 380MHz, maybe it would work a little higher also but I am not able to produce a higher clock yet :(
at first measuremens I got readings like 899MHz but that was a hoax - bad experiment. 380MHz is verified stable working - in S3 -4 speed the similar number is 420MHz so here the 10% decrease
I was then looking at max-toggle rate for S3e, and timings specs and did not find any that info so was wondering a little whats up
Antti, if you want to test or compare the internal fabric speed, you can just build a ring oscillator inside, divide the frequency down in a couple of flip-flops, and observe the frequency on the output pin. Build the oscillator out of a reasonable chain with only one inversion in it. That way you can include or exclude certain routings, carry chains, etc. And the frequency counter gives you tremendous accuracy and resolution. Peter Alfke
"Peter Alfke" schrieb im Newsbeitrag news: snipped-for-privacy@o13g2000cwo.googlegroups.com...
hehe, ;) this is the way I am doing it for some already !!!
this is great tool to measure things with virtually any accuracy .. I am using Pentium cycle counter to measure frequencies on such FPGA systems that do not have any known reference clock, I have a speical multichannel jtag-bscan connected freqency measurement ip core and analyzer host software,
BTW it is included in the Spartan3e sample pack standalone utility to measure the silicon oscillator :)
there are some tricks with the ring oscillator, for repeatable results it should be (r)LOC ed to primitives that produces always same routing, also some 'variants' tend to swing at too high frequency so high that it doesnt get a single flip flop to toggle even if there is direct route and one single load.
so I have different oscillators, a good one for Spartan3/e is a "2 LUT delay" oscillator, it runs at around 400MHz in S3/e the output is divided by
2 in the same slice and only divied by 2 output is used.
on Virtex-4 this oscicllator is unuseable - runs to fast, so some more LT delays need to be in chain to get useable frequency.
If they did mix parts on a wafer, it would be complete parts of specific sizes, not something that can be diced up in various ways.
That's called a shuttle run or multi-project wafer (MPW). It's normally done for test chips or very low volume production. I wouldn't expect that Xilinx would be doing that even for ES silicon, though they might well do it for pre-ES design testing.
Over a broad range of applications, a Spartan-3E FPGA is _in general_ the same performance or mildly faster than a Spartan-3 FPGA using the slowest speed grade for both. These tests were done using worst-case speed file numbers, which are more pessimistic than actual silicon.
Hopefully, this shouldn't be too surprising as Spartan-3 and Spartan-3E FPGA are built on the same 90 nm process technology using the same manufacturing facility.
I would expect some variation comparing actual silicon on two different devices. The data sheet tells you the slowest silicon we're allowed to ship, but the actual device likely is faster, especially at room temperature and nominal voltage.
That said, if you compare the Tilo specification for the Spartan-3 and Spartan-3E families in their respective data sheets, you will see about
150 ps of delay difference.
Spartan-3: Tilo on a -4 device = 0.61 ns
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[Page 79]
Spartan-3E: Tilo on a -4 device = 0.76 ns
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[Page 133]
I wouldn't focus on a specific parameter per se, as your path delay will include other timing parameters as well. For example, Spartan-3E generally has faster flip-flop clock-to-output delays and faster interconnect. In the wash, Spartan-3E _generally_ is at or about the same performance.
--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs
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--------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.
"Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" schrieb im Newsbeitrag news: snipped-for-privacy@g44g2000cwa.googlegroups.com...
Hi Steve,
it was really my fault - I have downloaded DS312.PDF zillion times and this time when I was now looking for timing data I happened to open DS312.PDF dated May 2005 so in that outdated version there was no timing data.
my measurements includes delay of 2 LUT, eg 2x Tilo + 2x interconnect within the same switchbox (no routing only switchbox), the result of that measurement indicated the Tilo increase exactly to the amount as as it is stated in the datasheet. Actually a little less, so the interconnect (swithcbox) may really be a little faster.
would I have had the latest datasheet open when looking at timing data I would not have been surprised, my mistake, in the feature I will try to use only fresh Xilinx datasheets to avoid using outdated versions.
Do you know about the speedprint utility? I don't know if it's part of WebPack but it certainly is part of the mainstream tools. On my unix platform, all I need is a "speedprint xc3s50" and I get the results for the faster speed grade device. I can select a -4 speed grade with the -s switch adding -s4 to the command line: "speedprint -s4 xc3s50" (if there is a -4 in this Spartan3 size).
I like being able to get the piece-parts to some of my "best case" timing values on critical logic without running through a full compile. I can look at different implementations (carry chain? MUXF5?) for critical logic without too much confusion. At first glance the value names may be a little confusing but there are ways to get some description on what they mean.
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