Hi, I am using xilinx 13.2 for synthesis and implementation of my design. I wanted to create RPMs of some small logic so that I can reuse it anywhere in my design by just instantiating. But I cannot find any relevant documentation on the internet, and the documentation I found is for previous versions using the floorplan method. Can anyone direct me to a proper documentation or some guide or link, that would be great.
Also, when I create RPMs and I map the components by hand, whenever i will instantiate it, the components will be placed in the same order or will they change depending on the complete design and routing?
Regards Muhammad Hassan
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It seems that you are stuck with the same problem as I have. There do not s= eem to many people here who have knowledge about hard macros and such.
Two links that are interesting:
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It seems that the design flow should be basically this:
- Write your component in VHDL
- Synthesize it for your FPGA
- Go to PlanAhead
- Define a PBLOCK for your component, so that you can constrain it in a sma= ll area
- Let ISE implement the design
- Go to FPGA Editor in Post-Map and Route
- Save your design first as a hard macro ! Make sure that you have a backup of this, because FPGA Editor has no undo= function
- Follow the instructions in the second link given
Since FPGA Editor works on large field, zooming in and out is very often ne= cessary, and markers are very small, tiny even.
E.g. 3. A green dot will appear over pin on the CLB/slice that had previous= ly been routed to that pad. Now, add an External Macro pin to this site; th= is will allow the pin to be instantiated in your code. (Note that if the IO= B was routed to two pins on a slice, you must give both pins a different na= me, or PAR will issue errors.)=20
You will see this green dot only when you zoom in on really deep on the sli= ce where the connection was.
This is currently how far I got (yesterday evening). The paper by Beckhoff = and Koch is well written, but understanding will only grow by using the too= ls.
Thanks a lot. But my problem got solved, I played around with RLOCs and of course people helped me a lot. I have made a small guide for making RPMs in verilog. If you want it maybe I can send it to you.
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You probably got more help through FPGARelated? Think I should join there too.
Even though we program in VHDL here, I gladly accept your offer. Send it to jurgen dot defurne at telenet dot be (replace where appropriate). Anything that can help with understanding the issues is welcomed.
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