Hello
How to implement on-chip ROM memory resource sharing in FPGA? I implemented discrete cosine transform core using parallel distributed arithmetic approach, in which hardware multipliers are substituted by precomputed MAC results stored in LUT/ROM. Single ROM instance is 64x14 bits. Problem is that the ROM must be replicated many times to enable high throughput (replicated 9 times for first DCT stage and replicated
11 times for 2nd stage after transposition). This ends up having more than 25kbits of ROM memory in the core, which is pretty big. I know there are dual port memories with dual read port capability, but this will 'only' halve resources needed. Any better ideas?Michal