I hope I'm posting it in the right groups. I've been designing for a while, but with minimal JTAG knowledge.
Q: Can I use JTAG interface to verify what I wrote into the SRAM, instead of the traditional read-back method?
My setup and the reason for wanting to do it this way is : An FPGA interfaces to a sync SRAM (QDR with separate write/read port). The FPGA can write to the SRAM using the processor interface, but does not have the read-back capability, because the read port from the SRAM goes elsewhere (no read-back capability there, either). Why do it this way? So that the each of the write/read data bus is point-to-point, without stubs on the board (150+Mhz). I could therotically bring the read bus back into the FPGA, then send it out again, but I'm fairly pin-limited. There are several SRAM interfaces, so whatever I do for each SRAM gets multipled by N. So, what I'd like to do is load the SRAM in a conventional manner, then test it via the JTAG interface. The amount of time it takes to verify doesn't matter.
The SRAM I'm thinking of using is Cypress, will be running it at
150+Mhz, and the device supports these JTAG instructions : EXTEST, IDCODE, SAMPLE Z, SAMPLE/PRELOAD, BYPASS (Preload isn't supported, actually). Looking at this, it looks like I need to use the FPGA to supply the read controls at a slower rate, to match JTAG speed, then use SAMPLE instruction. Or, am I way off base here? Would it get too messy and should I just provite the read-back path at the cost of higher pincount?Thank you in advance for any input/suggestion.
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