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Pci problems

  1. On a pci target a have on the pci bus signals pci_ad[31:0] and on the backend interface a have bkend_data[31:0] (for data r/w) and backend_adr[31:0] (for address r/w). If I interface a fifo 512x32bits I must connect bkend_dat[31:0] on the fifoin_dat[31:0]. But fifos don't have address lines. What shoud I must to do with bkend_ad[31:0] address lines?? (Put its on high-z ???) 2. If my pci target doesn't meet pci tsu
Reply to
Dan
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Impossible to say without knowing more about your PCI interface. However, if you're using non-addressable memory, what do you expect to do with the address line? Does it decode one register that you read repeatedly for data? Or does it act like a 'seek' on the fifo?

Reply to
Ben Jackson

I must to do some actions that are slowest that pci_clk and for that I use a fifo where I store temporary data. I use fifo_full and fifo_empty signals for make transactions between pci-target and fifo. I defined that fifo like a memory space with a base_address_register, and when a have a base_adr_hit for this space I must to write in the fifo (practicaly I must to write at the same address because fifo has no address lines).

Regards,

Reply to
Dan

So you are using the fifo to buffer for a memory interface that's not synchronous with the PCI bus? Then the base address would have to be stored where you're going to need it to determine where to put the output side of the fifo.

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Ben Jackson

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Reply to
Ben Jackson

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