Hello,
The PCI Express Base Specification v1.1 doesn't specify a reference clock; the reason is that PCI Express is designed to operate without a common reference clock between components. What the PCI Express Base Specification v1.1 does specify is the allowed ppm difference (+/- 300 ppm) on the unit interval (400 ps). Technically, you can use whatever reference clock you want, at whatever frequency you may desire, as long as your device's transmitter observes the UI specification and your device's receiver is able to lock onto a signal (from another device) that also observes the UI specification. In the most general case, this a pleisochronous interface.
While we are on the topic of common signals distributed to components, the PCI Express Base Specification v1.1 does not specify a common, distributed reset signal. It also does not specify a common, distributed power managment event signal. There are mechanisms to communicate these "events" in-band.
Now, all that being said, there is another document, the PCI Express Card Electromechanical Specification v1.1, which defines a standard card and slot form factor. One of the features of this form factor is the availability of a distributed reference clock that is nominally 100 MHz and has specified electrical characteristics. You can use it, or not. If you need some other frequency, like 125 MHz, or you need it in some other electrical signaling standard, you will need to provide for that conversion.
There are some significant advantages to using this reference clock. One is that you don't need to provide your own oscillator. Another advantage of using a common reference clock is that it turns what was a pleisochronous interface into something that is mesochronous which will, based on the specifications, tolerate the use of spread spectrum clocking on the reference clock. I am also told that this arrangement enables CDR circuits in receivers to lock much more quickly, facilitating low latency exits from PCI Express power saving states. I think that's because the lock to data step doesn't have far to go from the lock to reference, but I don't design PLLs so don't quote me on that.
The PCI Express Card Electromechanical Specification v1.1 also defines a reset signal, PERST#, and a power management event signal, WAKE#. These provide an alternate side-band (versus in-band) mechanism for signaling these events. Their operation and use is described in this separate document because they are NOT part of the base specification.
Eric Crabill Xilinx, Incorporated