I have built a prototyp board with wires between the FPGA and an external component. With the scope I can see glitches (looks like from crosstalk when switching other signals) and multiple transitions are detected by the FPGA when switching signals. Looks like the noise is < 200 ns. The period of the wanted signal is > 3 us. I think with a PCB there would be less problems, but there is lots of space left inside the FPGA, so it should be possible enhance the signal with logic so that it works even with the noisy wired prototype. What do you do normally to solve this kind of problems?
My idea is to use a low-pass filter: a n bit counter, which is incremented with system clock, if the input signal is 1 and decremented otherwise. If all n bits are 1, the counter is not incremented and if all bits are 0, it is not decremented. If the highest bit is set, then the sampled signal is considered as 1, otherwise as 0. I could encapsulate this function within a VHDL entity, so it is easy to use it for multiple input signals and maybe a generic for specifying n.